Abstract: The present invention discloses a precharge circuit for preventing undesired output pulses caused by the current sensing circuit of the flash memory devices. The access time of the read-cycle also can be decreased after the undesired output pulses are completely removed. Basically, the circuit disclosed by the invention encompasses the current mirror and the cell array as conventionally; a control circuit, a voltage detector and a precharge circuit to remove the undesired output pulses. The control circuit couples with the current mirror, the voltage detector, and the precharge circuit. The current mirror is used to generate output waveform. The precharge circuit couples with the cell array with a bit line, and pre-charges the voltage level of the bit line to a predetermined expected value. The control circuit controls the precharge circuit to precharge the bit line when the read-cycle starts. Whole the current sensing circuit keeps disable until the voltage level of the bit line rises to an expected value.

Abstract: The present invention discloses a system and method for controlling the dispensing of a fine liquid for coating or other applications, by detecting the volume of liquid dispensed when coating a single workpiece and sending a signal to a controller to disable the dispensing when an insufficient volume of liquid is being dispensed. In a preferred embodiment, the fine liquid is spin-on-glass (SOG) used in semiconductor processing machinery during wafer fabrication and the the SOG volume dispensed when coating a semiconductor wafer is measured using a weight measurement instrument, e.g., an electronic scale capable of 0.1 gm. accuracy, which outputs a weight signal that is input, along with a dispenser condition signal from the SOG dispensing machine, to a programmable logic controller (PLC). A set point is selected to produce a desired weight of dispensed liquid, e.g., 1.7 gms. when 2 ccs. are desired, and is programmed into the PLC.

Abstract: The present invention discloses a method for etching a silicon surface or forming alignment marks in a silicon substrate by first coating the substrate with an oxide layer, then depositing and patterning a photoresist layer on top of the oxide layer and forming the alignment marks by a dry etching process utilizing fluorine/oxygen etchant chemistry for the simultaneous etching of the two layers in a single process wherein the oxide layer prevents the contamination of the silicon wafer by any silicon particles formed.

Abstract: The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process.

Abstract: The present invention discloses a method and apparatus for eliminating air bubbles from a liquid dispensing line by utilizing an air bubble tank positioned and connected in fluid communication between a liquid reservoir and an electric pump for feeding the liquid. The air bubble tank cumulates air bubbles in an upper portion of the tank cavity and allows a liquid flow which is substantially free of air bubbles to be outputted from an outlet positioned adjacent to the bottom of the tank to a process machine, while the air bubbles are exhausted out of the tank on a predetermined frequency.

Abstract: An apparatus and method are disclosed for enhancing the operation of ESD protective circuits in a VLSI chip, having first and second CMOS devices therein which prevent damage due to ESD events, the first device being connected between a Vss contact and an I/O Pad contact and the second device being connected between a Vcc contact and the I/O Pad contact, and including diffusions in the chip that form a first diode which turns ON when negative ESD stresses develops between one of the first and second contacts and the I/O Pad contact, and which form a NPN transistor and a second diode that turn ON when positive ESD stresses develop between one of the first and second contacts and the I/O Pad contact, and additionally having the Vss and Vcc sources capacitively coupled.

Abstract: An automatic supervision system using an ion beam map generated by an ion implantation machine during an ion implantation process a feature extraction circuit and a data converter. The feature extraction circuit receives a beam current signal and a display blanking signal from the ion implantation machine, and extract features of the ion beam map. The data converter is coupled to the feature extraction circuit and converts the features into indexes indicative of the alignment and symmetry of beam maps. The data converter also compares the indexes to index values or symptoms of known abnormal ion beam scanning, which allows the data converter to recognize abnormal ion beam scanning and indicate the proper corrective action to adjust the ion beam scanning. Thus, the two-dimensional beam map recognition analysis is reduced to a one-dimensional feature analysis, thereby simplifying the beam map recognition process.

Abstract: The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

Abstract: A photoresist supplying system for used in a semiconductor fabrication, the system includes a photoresist holder for storing photoresist. A first gas supplier is connected to the photoresist holder for providing gas to the photoresist holder to force the photoresist out of the photoresist holder. A buffer is connected to the photoresist holder via an input terminal to exhaust the gas, the photoresist is output by an output terminal of the buffer. A first valve is connected to the output terminal of the buffer for controlling the flowing rate of the photoresist. A second valve is connected to the buffer to drain the gas collected by the space. A pumping apparatus is connected to the first valve via an input terminal to suck the photoresist. A filter is connected to the pumping apparatus to filter out the impurity in the photoresist. A vibrator is set in the photoresist supplying system to hold the filter for eliminating bubble.

Abstract: The present invention discloses a method for marking a wafer surface with minimized particulate contamination problem and further, the method is compatible with a chemical mechanical polishing method for planarization. An identification mark can be made on the non-patterned side of a wafer by a high energy laser beam either with or without an insulating layer deposited on top of the wafer. The method can also be carried out by first providing an identification mark on a non-patterned surface of the wafer and then, after all fabrication processes have been conducted on the patterned side of the wafer and a planarization process is conducted by a chemical mechanical polishing method, the identification mark on the backside of the wafer can be automatically read and then reproduced on the patterned side of the wafer prior to the shipment of the wafer to a customer or to a packaging facility.

Abstract: A buffer circuit for generating full-swing output is disclosed. The circuit includes a pull-up circuit for transferring a supply voltage to an output line in response to a first state of an input signal. A pull-down circuit is used to pull the output line down to a ground in response to a second state of the input signal. A control circuit is used to activate only one of the pull-up circuit and the pull-down circuit respectively in response to the first state and the second state of the input signal. Further, a charge-pump circuit responsive to the input signal and a clock signal is used to generate a charge-pump voltage to an input of the pull-up circuit so that the supply voltage is transferred to the output line.

Abstract: A power-on reset circuit (28) is disclosed. The circuit includes a first stage circuit (30) and a second stage circuit (32). The first stage circuit includes an input terminal coupled to receive an input signal, a latch for detecting a power-on condition, and an output terminal for providing a first stage circuit output signal. The first stage circuit output signal remains in a first state after detection of the power-on condition. The second stage circuit includes an input terminal coupled to receive the first stage circuit output signal, a latch for detecting the power-on condition, and an output terminal for providing a second stage circuit output signal. The second stage circuit output signal remains in the first state after detection of the power-on condition.

Abstract: The present invention discloses a method for forming a zig-zag bordered opening in a semiconductor structure such that the film stress in a barrier/glue layer of TiN can be significantly reduced to eliminate the occurrence of volcano defect in which delamination or peeling-off of the TiN layer from the contact opening occurs. The method can be easily carried out by providing a mask that has a desirable zig-zag pattern during a photomasking step performed on the semiconductor device.

Abstract: An apparatus and method are disclosed for enhancing the operation of an ESD protective circuit in a VLSI chip with a combination of elements for an SCR that lower the turn-on voltage of the SCR below the oxide breakdown voltage of the CMOS devices in the VLSI circuits. A low voltage trigger source is provided for the SCR by forming an N+-P-LDD junction between the SCR and a CMOS device incorporated therein. The prior art N-channel device used in triggering the known LVTSCR is modified by removing the rate electrode and thin oxide and implanting, adjacent the N+ drain region, a P-type lightly doped drain (P-LDD) region in the substrate to form the N+-P-L.DD junction. The turn-on voltage of this N+-P-LDD junction can be made lower than the oxide breakdown voltage of the CMOS devices by adjusting the P-LDD dosage. Junction breakdown causes a forward bias resulting in turn ON of the PNP bipolar device followed by turn ON of the interconnected NPN bipolar device to produce the high current flow through the SCR.

Abstract: The present invention provides a method of forming an oxide dielectric layer on a tungsten silicide gate structure in a furnace oxidation process by first depositing a thin layer of amorphous silicon on top of the refractory metal silicide gate structure such that the refractory metal silicide is not damaged by the oxidant during the furnace oxidation process. For a tungsten silicide gate structure, a thin layer of amorphous silicon between about 10 .ANG. and about 100 .ANG. thick can be suitably used for such purpose.

Abstract: The present invention discloses a method for in-situ cleaning a reactive ion etching (RIE) chamber after a silicon nitride etching process by maintaining a vacuum and a radial frequency power in the chamber while flowing a chlorine gas into the chamber at a sufficient flow rate. The chlorine gas cleaning step can be integrated into the process recipe for the etching process without significantly affecting the cycle time and the yield of the process.

Abstract: The present invention discloses a method for coating a polyimide precursor on an electronic structure incorporating the use of a silicon coupling agent without any bubble defect in the film deposited. The method can be carried out by flowing at least one inert gas through a deposition chamber and thereby keeping the relative humidity in the chamber at below 25% to carry away the formation of any water molecules and water vapor to prevent the formation of bubbles in the film deposited.

Abstract: A mobile work-in-process parts tracking system includes a vehicle for transporting the work-in-process parts stored in containers, a tag mounted on the container and a tag reader mounted on the vehicle for reading the tag and outputting data to a data concentrator which accepts data from a plurality of tag readers and then outputting data in a single cable by removably connecting to a data distributor mounted in the factory floor, such that the location of the WIP parts transported on the vehicle can be tracked and monitored.

Abstract: The present invention discloses a method for mounting a peripheral device, such as a wafer loading device, to a semiconductor process tool that includes sensor means in the mounting surface of the peripheral device such that improper mounting between the two components can be detected and a signal can be sent out to a host computer to disable the peripheral device and to stop its motion and thus prevent any damages to the components or the substrates it carries. The peripheral device may further include spring means mounted in its mounting surface to enable the peripheral device to be pushed away from the process tool to provide a visual indication to a machine operator when the two components are not properly mounted together.

Abstract: A self-setup non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate having a first input terminal coupled to receive an inverted signal of the primary clock signal. Further, a second logic gate is provided, having a first input terminal coupled to receive the primary clock signal. A first programmable delay portion is used to delay an output signal from the first logic gate an amount of time according to the selection signal, and a second programmable delay portion is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. Therefore, a first clock signal is generated from the output of the first logic gate, and a second clock signal is generated from the output of the second logic gate.