Abstract: A system includes a dispatching system and at least one processor. The dispatching system is configured to provide dispatching preferences indicating that tools feedback preferences thereof for at least one lot. The processor is coupled to the dispatching system and at least one memory. Computer program code encoded in the memory is executed by the processor to cause the system to process the lot using at least one of the tools with utilization of a tool-lot relationship that is generated based on the dispatching preferences. A non-transitory computer readable medium and a method are also disclosed herein.

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

Abstract: A package structure includes a first semiconductor die, an insulating encapsulant, a plurality of first through insulator vias, a plurality of second through insulator vias, and a redistribution layer. The insulating encapsulant is encapsulating the first semiconductor die. The first through insulator vias are located in a central area of the insulating encapsulant surrounding the first semiconductor die. The second through insulator vias are located in a peripheral area of the insulating encapsulant surrounding the plurality of first through insulator vias located in the central area, wherein an aspect ratio of the plurality of second through insulator vias is greater than an aspect ratio of the plurality of first through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the first semiconductor die, the plurality of first through insulator vias and the plurality of second through insulator vias.

Abstract: A photodetector is provided. The photodetector includes a semiconductor layer, a first superlattice structure in the semiconductor layer, and a light absorption material above the first superlattice structure. The first superlattice structure includes vertically stacked pairs of silicon layer/first silicon germanium layer. The first silicon germanium layers are made of Si1-xGex, and xi s the atomic percentage of germanium and 0.1?x?0.9.

Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.

Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.

Abstract: A structure including a semiconductor die, a conductive pillar, and an insulating encapsulation is provided. The conductive pillar includes a first pillar portion and a second pillar portion disposed on the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. The insulating encapsulation laterally encapsulates the semiconductor die and the conductive pillar.

Abstract: Disclosed is a physical unclonable function generator circuit and method.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.

Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.

Abstract: A method is provided. Plural semiconductor fins are formed on a substrate, and plural trenches each of which is formed between two adjacent semiconductor fins. A silicon liner layer is deposited to be conformal to the semiconductor fins and the trenches. The silicon liner layer is deposited by using a silane compound. Then, an oxide layer is deposited on the silicon liner layer to fill the trenches and cover the semiconductor fins, in which depositing the oxide layer forms water in the oxide layer. Next, a surface of the silicon liner layer is reacted with the water, so as to remove the water from the oxide layer.

Abstract: A method for cleaning a reticle includes rotating the reticle, providing a cleaning liquid to clean the reticle, detecting a static charge value on the reticle during rotating the reticle, and reducing static charges on the reticle in response to the detected static charge value. Hence, the electrostatic discharge (ESD) occurred to the reticle can be prevented.

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.

Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.

Abstract: A method includes forming an interlayer dielectric (ILD) and a gate structure over a substrate. The gate structure is surrounded by the ILD. The gate structure is etched to form a recess. A first dielectric layer is deposited over sidewalls and a bottom of the recess and over a top surface of the ILD using a first Si-containing precursor. A second dielectric layer is deposited over and in contact with the first dielectric layer using a second Si-containing precursor different from the first Si-containing precursor. A third dielectric layer is deposited over and in contact with the second dielectric layer using the first Si-containing precursor. Portions of the first, second, and third dielectric layer over the top surface of the ILD are removed.

Abstract: Fin-based well straps are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin structure doped with a first dopant concentration of the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin structure doped with a second dopant concentration of the first type dopant and second source/drain features of the first type dopant. The second dopant concentration is greater than (for example, at least three times greater than) the first dopant concentration.

Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.