Abstract: An electronic device is disclosed that includes an output device and a detection circuit. The output device is coupled to an output pad, and is turned on according to a protection signal. The detection circuit is configured to detect a voltage level of a control node, to generate the protection signal based on the detected voltage level, and to switch the voltage level to a predetermined voltage level according to the detected voltage level.

Abstract: A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the first transistor. The first PODE device is adjacent to a drain/source region of the second transistor. A control end of the first PODE device is electrically coupled to a drain/source end of the second transistor.

Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.

Abstract: Methods for forming image sensor structures are provided. The method includes forming an isolation structure in a substrate and forming a first light sensing region and a second light sensing region. The method further includes forming a first gate structure and a second gate structure, and the first gate structure and the second gate structure are positioned at a front side of the substrate. The method further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate. The method further includes forming a contact trench through the interlayer dielectric layer and forming a contact in the contact trench.

Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.

Abstract: A semiconductor structure includes a substrate, a first semiconductor fin, a second semiconductor fin, and a first lightly-doped drain (LDD) region. The first semiconductor fin is disposed on the substrate. The first semiconductor fin has a top surface and sidewalls. The second semiconductor fin is disposed on the substrate. The first semiconductor fin and the second semiconductor fin are separated from each other at a nanoscale distance. The first lightly-doped drain (LDD) region is disposed at least in the top surface and the sidewalls of the first semiconductor fin.

Abstract: The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and associated processing methods. In some embodiments, the flash memory device includes a gate stack separated from a substrate by a gate dielectric. The gate stack includes a control gate separated from a floating gate by a control gate dielectric. An erase gate is disposed on a first side of the gate stack and a word line is disposed on a second side of the gate stack that is opposite to the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. A word line height at the outer side is smaller than an erase gate height.

Abstract: A microelectromechanical systems (MEMS) structure with a cavity hermetically sealed using a mask layer is provided. A capping substrate is arranged over a MEMS substrate, which includes a movable element. The capping substrate includes the cavity arranged over and opening to the movable element, and includes a seal opening in fluid communication with the cavity. The mask layer is arranged over the capping substrate. The mask layer overhangs the seal opening and laterally surrounds a mask opening arranged over the seal opening. A seal layer is arranged over the mask layer and the mask opening. The seal layer is configured to hermetically seal the cavity. A method for manufacturing the MEMS structure is also provided.

Abstract: An image sensor structure and a method for forming the same are provided. The image sensor structure includes a first substrate including a first radiation sensing region and a first interconnect structure formed over a front side of the first substrate. The image sensor structure further includes a second substrate including a second radiation sensing region and a second interconnect structure formed over a front side of the second substrate. In addition, the first interconnect structure is bonded with the second interconnect structure.

Abstract: An image sensor is provided including a substrate, an array of photosensitive units, a grid and a plurality of color filters. In the image sensor, the grid has a first portion and a second portion disposed on the first portion. The second portion of the grid can cause reflection or refraction of incident lights targeted for one image sensor element back into the same image sensor element, so as to avoid crosstalk occurred. Further, a method for manufacturing the image sensor also provides herein.

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.

Abstract: The present disclosure provides a three dimensional integrated circuit having a plurality of dies. Each die includes a trigger line common to the other dies, and an ESD detection circuit coupled to the common trigger line and to a first power line common to the other dies, wherein when the ESD detection circuit of one of the plural dies detects an ESD event, the ESD detection circuit is configured to generate a control signal to the common trigger line to control a power clamp in each of the plural dies to clamp an ESD event to the common first power line or a second power line.

Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.

Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer includes metal ions.

Abstract: Some embodiments relate to high density capacitor structures. Some embodiments include a first trench capacitor, a second trench capacitor and an interconnect structure. The first trench capacitor includes a first capacitor plate disposed in a plurality of trenches in a semiconductor substrate, and a second capacitor plate disposed in the plurality of trenches and separated from the first capacitor plate by a first capacitor dielectric along bottom and sidewall surfaces of the plurality of trenches. The second trench capacitor is disposed over the first trench capacitor. The second trench capacitor includes the second capacitor plate, and a third capacitor plate disposed in the plurality of trenches and separated from the second capacitor plate by a second capacitor dielectric. The interconnect structure connects the first capacitor plate and the third capacitor plate such that the first and second trench capacitors are in parallel.

Abstract: The present disclosure relates to voltage regulation techniques. In some embodiments, a voltage regulator is configured to regulate an output voltage based on a reference voltage. The voltage regulator comprises an analog-to-digital converter, an encoder, a decoder and a power stage. The analog-to-digital converter receives the reference voltage and an output voltage of the voltage regulator and provides a digital error signal. The encoder is coupled to the analog-to-digital converter output and configured to provide a multi-bit digital control signal based upon a present value of the digital error signal, a plurality of pre-determined coefficients, and a plurality of previous values of the digital error signal. The decoder is coupled to the encoder and configured to generate a plurality of control signals based on the multi-bit digital control signal. The power stage comprises a plurality of power cells which are coupled to a power supply and which receive the plurality of control signals, respectively.

Abstract: A semiconductor device includes a substrate, source/drain contacts, gate structures, conductive elements, and a first stop layer. The substrate has source/drain regions formed therein. The source/drain contacts are over the substrate and each of the source/drain contacts is electrically connected to the respective source/drain region. The gate structures are arranged in parallel on the substrate. The source/drain regions are arranged at opposite sides of the gate structures. Each of the gate structures is sandwiched between two most adjacent source/drain contacts. The conductive element is on the source/drain contacts and crosses over the gate structures. The conductive element is overlapped with at least one gate structure and at least two most adjacent source/drain contacts and is electrically connected to the at least two most adjacent source/drain contacts.

Abstract: A method includes depositing a first dielectric structure over a non-insulator structure, removing a portion of the first dielectric structure to form a via opening, filling the via opening with a dummy structure, depositing a second dielectric structure over the dummy structure, etching a portion of the second dielectric structure to form a trench over the dummy structure, removing the dummy structure from the via opening, and filling the trench opening and the via opening with a conductive structure, wherein the conductive structure is electrically connected to the non-insulator structure.