Patents Assigned to Taiwan Semiconductor Manufacturing
  • Method for forming semiconductor device structure
    Patent number: 9871137
    Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yeh Huang, Kai-Hsiang Chang, Chih-Chen Jiang, Yi-Wei Peng, Kuan-Yu Lin, Ming-Shan Tsai, Ching-Lun Lai
  • Lithography process
    Patent number: 9869939
    Abstract: A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shinn-Sheng Yu, Anthony Yen
  • Semiconductor arrangement having an overlay alignment mark with a height shorter than a neighboring gate structure
    Patent number: 9870998
    Abstract: Among other things, one or more semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. A layer, such as a poly layer or an inter layer dielectric (ILD) layer, is formed over a substrate. A photoresist mask is formed over the layer. The photoresist mask comprises an open region overlaying a target region of the layer and comprises a protection region overlaying a second region of the layer. An etching process is performed through the open region to reduce a height of the layer in the target region in relation to a height of the layer in the second region because the protection region inhibits the etching process from affecting the layer in the second region. A first structure, having a first height, is formed within the target region. A second structure, having a second height greater than the first height, is formed within the second region.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien, Tzong-Sheng Chang
  • SRAM circuits with aligned gate electrodes
    Patent number: 9871046
    Abstract: A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge region in combination include first gate electrodes having a uniform pitch. A word line driver abuts the SRAM cell edge region. The word line driver includes second gate electrodes, and the first gate electrodes have lengthwise directions aligned to lengthwise directions of respective ones of the second gate electrodes.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang, Ren-Fen Tsui, Shih-Chi Fu, Yen-Huei Chen
  • Method of forming an isolation structure in a well of a substrate
    Patent number: 9871105
    Abstract: A method includes forming an isolation structure in a well of a substrate. A portion of the isolation structure protrudes from a top surface of the well. The isolation structure is partially removed, thereby forming a modified isolation structure. An upper surface of the modified isolation structure is lower than the upper surface of the substrate.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Chih Chou, Kong-Beng Thei
  • Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof
    Patent number: 9869928
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chih-Tsung Shih, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Solid precursor delivery method using liquid solvent for thin film deposition
    Patent number: 9869018
    Abstract: A method of solid precursor delivery for a vapor deposition process is provided. In some embodiments, a precursor ampoule is provided including a solid precursor arranged in the precursor ampoule. A solvent is added to the precursor ampoule including one or more ionic liquids to dissolve chemical species of the solid precursor and to form a liquid precursor. A carrier gas is applied into the liquid precursor through an inlet of the precursor ampoule. A gas precursor is generated at an upper region of the precursor ampoule by vaporization of the liquid precursor. The chemical species of the solid precursor are delivered into a vapor deposition chamber by the carrier gas. The chemical species of the solid precursor is deposited onto a substrate within the vapor deposition chamber.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Chieh Lee, Chi-Ming Yang, Lin-Jung Wu
  • Trench structure of semiconductor device having uneven nitrogen distribution liner
    Patent number: 9871100
    Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin, Ying-Lang Wang, Wei-Ken Lin, Chuan-Pu Liu
  • FinFETs with nitride liners and methods of forming the same
    Patent number: 9870956
    Abstract: An integrated circuit structure includes a semiconductor substrate, which includes a semiconductor strip. A Shallow Trench Isolation (STI) region is on a side of the semiconductor strip. The STI region includes a first portion comprising an oxide and a second portion free from oxide. The second portion separates the first portion from the semiconductor substrate. A semiconductor fin is over and aligned to the semiconductor strip, wherein the semiconductor fin is higher than a top surface of the STI region.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Gin-Chen Huang, Ching-Hong Jiang, Sey-Ping Sun, Clement Hsingjen Wann
  • Growing III-V compound semiconductors from trenches filled with intermediate layers
    Patent number: 9870920
    Abstract: A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsin Ko, Cheng-Hsien Wu, Clement Hsingjen Wann
  • Semiconductor device and manufacturing method thereof
    Patent number: 9871101
    Abstract: A semiconductor structure, and methods for forming the semiconductor device are provided. In various embodiments, the semiconductor device includes a substrate, source/drain regions over the substrate, a plurality of nanowires over the substrate and sandwiched by the source/drain regions, a gate dielectric layer surrounding the plurality of nanowires, and a gate layer surrounding the gate dielectric layer.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gerben Doornbos, Chun-Hsiung Lin, Chien-Hsun Wang, Carlos H. Diaz
  • Metal gate scheme for device and methods of forming
    Patent number: 9871114
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau
  • Chip package with thermal dissipation structure and method for forming the same
    Patent number: 9870975
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first package structure including a first semiconductor die that has a first side and a second side opposite thereto. The chip package also includes a package layer partially or completely encapsulating the first semiconductor die, and a conductive feature in the package layer. The chip package further includes a first heat-spreading layer over the first side of the first semiconductor die and a first cap layer on the first heat-spreading layer.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hua Wang, Po-Yao Lin, Shu-Shen Yeh, Kuang-Chun Lee, Shin-Puu Jeng, Shyue-Ter Leu, Cheng-Lin Huang, Hsiu-Mei Yu
  • Formation of copper layer structure with self anneal strain improvement
    Patent number: 9870995
    Abstract: A copper layer structure includes a first copper layer, a second copper layer and a carbon-rich copper layer. The second copper layer is disposed over the first copper layer. The carbon-rich copper layer is sandwiched between the first copper layer and the second copper layer. A carbon concentration of the carbon-rich copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-Nan Nian, Shiu-Ko Jangjian, Chi-Cheng Hung, Yu-Sheng Wang, Hung-Hsu Chen
  • Structure and method for a SRAM circuit
    Patent number: 9870815
    Abstract: The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (SRAM) cell having a first cell size; and a second SRAM cell having a second cell size greater than the first cell size. The first SRAM cell includes first n-type field effect transistors (nFETs) each having a first gate stack. The second SRAM cell includes second nFETs each having a second gate stack different from the first gate stack.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Semiconductor device and manufacturing method thereof
    Patent number: 9870926
    Abstract: A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1-xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1-yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1-zGez is formed on the second epitaxial layer. Z is smaller than y.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Min Huang, Hsiu-Ting Chen, Shih-Chieh Chang
  • Contact area design for solder bonding
    Patent number: 9871013
    Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Chun Tsai, Yu-Feng Chen, Tin-Hao Kuo, Chen-Shien Chen, Yu-Chih Huang, Sheng-Yu Wu
  • Power MOSFETs and methods for manufacturing the same
    Patent number: 9871134
    Abstract: A semiconductor device and the method of manufacturing the same are provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yogendra Yadav, Chi-Chih Chen, Ruey-Hsin Liu, Chih-Wen Yao
  • STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20180012769
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer. A gate dielectric layer of the gate stack adjoins the first layer and the second layer.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jean-Pierre COLINGE, Carlos H. DIAZ
  • THINNING PROCESS USING METAL-ASSISTED CHEMICAL ETCHING
    Publication number: 20180012880
    Abstract: Methods for forming a chip package are provided. The method includes providing at least one carrier substrate including first semiconductor dies mounted thereon. The method also includes forming a first noble metal layer including nanopores irregularly distributed therein to cover each one of the first semiconductor dies. The method further includes immersing the carrier substrate with the first semiconductor dies into an etchant solution including a fluoride etchant and an oxidizing agent, so that each one of the first semiconductor dies covered by the first noble metal layer is thinned.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Chun YANG, Yi-Li HSIAO, Tung-Liang SHAO, Chih-Hang TUNG, Chen-Hua YU