Abstract: In a D/A converting apparatus which provides a converted analog signal at its output terminal by selectively yielding one or more currents from one or more current sources in accordance with an input digital signal, the current sources are selectively actuated to output the currents and an error in the current of each selected current source is obtained from the output derived at the output terminal in response to the outputting of the current. From the current error of each current source is computed a final error corresponding to each input digital signal and corrected data corresponding to the final error is stored in a corrected data memory, which is read out by the input digital signal. The output thus read out is converted into an analog signal, whereby a correct converted output is obtained.

Abstract: A clocked logic circuit operates in synchronism with a clock and is supplied with an input binary signal asynchronously with the clock for issuing an output binary signal. A phase detector circuit produces a phase difference signal indicating into which of k divided phase regions of one period of the clock falls, the phase difference between the input binary signal and the clock. The phase difference signal is delayed by a matching delay means for a delay approximately equal to a delay of the clocked logic circuit. An output binary signal from the clocked logic circuit is given a delay corresponding to one of the k phase regions designated by the delayed phase difference signal, and the delayed output binary signal is issued to an output terminal.

Abstract: A set value of a frequency setting register is accumulated upon each occurrence of a clock signal, and a waveform memory is read out by using the accumulated value as an address. In the waveform memory, amplitude data of one cycle of the waveform of a burst signal to be generated are stored at fixed phase intervals. The output read out of the waveform memory is converted into an analog signal. A wave-number counter counts the number of times the amplitude data of one cycle is read out of the waveform memory and, when having counted by a preset number of waves, yields a wave-number counting end signal. After the occurrence of the wave-number counting end signal, a phase counter counts clock signals, and, when the count value of the phase counter reaches a value corresponding to a preset end phase, the generation of the burst signal is stopped.

Abstract: A logic analyzer applies test pattern signals from a pattern generator to a circuit under test and sequentially reads logic outputs into a memory. The output from the circuit under test when it reaches a predetermined logic state is input as an external control signal into the logic analyzer. A change command is generated from the pattern generator in relation to the generation of the test pattern signal. When the change command and the external control signal are obtained at the same time, and flow of the generation of the test pattern signals is changed to a predetermined flow.

Abstract: Logic output data of a plurality of channels simultaneously obtained from a circuit under test are sequentially input in a memory, and after inputting a predetermined amount of such data, they are compared with corresponding expected values. The input data are divided into blocks, each including a plurality of data. Whether a mismatch is present in the comparison results for each block is indicated by a respective block element, and such block elements are displayed in a predetermined arrangement. It is also possible to provide a conventional list display including the input timing corresponding to the comparison results in which a mismatch is present.

Abstract: A synchronizing gate signal is generated in synchronism with an input signal or a clock signal, and first and second gates are opened by the synchronizing gate signal. The input signal having passed through the first gate is counted by a first counter circuit, and the clock signal having passed through the second gate is frequency-divided by a divide-by-10.sup.n frequency divider. An output from the frequency divider is counted by a second counter means. The synchronizing gate signal is generated under the control of a control circuit, and is prevented from being generated when the output from the frequency divider is applied to the control circuit. The n in the frequency-division ratio 1/10.sup.n of the frequency divider and a maximum count P of a third counter circuit are determined from a count of the third counter circuit, a preset measurement accuracy, and a period of the clock signal at the time one output is produced from the frequency divider, the n being set in the frequency divider.

Abstract: In a main pattern memory are stored an increment command pattern and an enable control pattern in addition to test patterns. The main pattern memory is read out with an address from an address control circuit. The increment command pattern thus read out of the main pattern memory instructs incrementing of an address pointer, and a partial pattern memory is read out according to the contents of the address pointer. In accordance with the enable control pattern read out of the main pattern memory, a gate circuit is controlled to open, through which the output of the partial pattern memory is passed, and bits of the passed output are each ORed, by an OR circuit, with the corresponding bits of the test pattern read out of the main pattern memory, providing the ORed output as a test pattern.

Abstract: Logic data (input data) is sequentially supplied to a data memory using sampling pulses and the input data is written into the data memory at an address specified by an address signal from an address counter which advances by one upon each occurrence of the sampling pulse. The input data and an output trigger word from a trigger word register are compared by a trigger word detector, and when coincidence is detected therebetween, a coincidence signal is generated, which signal is delayed by a delay circuit by a value corresponding to output delay data from a delay register. The delayed output is provided as a stop signal. By the stop signal the address counter is preset to a leading address of a storage area of the data memory into which data is to be stored and the next trigger word is provided from the trigger register. Further, the next delay data is provided from a delay register and the next store number is output from a store-number register.

Abstract: When a trigger clock is input, its leading and trailing edges are detected, and first and second oscillators are started to oscillate by the leading and trailing edge detected outputs, respectively. The first and second oscillators oscillate at the same oscillation frequency, which is determined by data set in period setting means. A flip-flop is set by the output of the first oscillator and reset by the output of the second oscillator and the flip-flop output is provided as multi-clock pulses. The number of multi-clock pulses from the flip-flop is counted by a clock counter, and when it is detected by a stop detector that the clock counter has counted to a preset value, the first and second oscillators are stopped, by the detected output, from oscillation.

Abstract: An input time signal and clock pulses are provided to a gate, from which the clock pulses are output for a period of time corresponding to the duration of the input time signal, and the clock pulses are applied to a time counter. The time counter is preset, for each measurement, by to a time corresponding to minimum and maximum values of a time interval to be measured and yields a validity signal for a period of time therebetween. The minimum and maximum values of the time interval to be are referenced from the start of the supply of the clock pulses. It is decided and only for whether the validity signal exists at the end of the input time signal, an input time signal that ends during the duration of the validity signal, is its measured duration utilized as valid data.

Abstract: First and second input signals are waveform-shaped into rectangular wave signals and, in a period measuring mode, one of the rectangular wave signal is input into a time interval measuring circuit and clock pulses are counted during the period of the rectangular wave signal. In a time interval measuring mode, the clock pulses are counted by the time interval measuring circuit over the time interval between one edge of the one rectangular wave signal and the corresponding edge of the other rectangular wave signal, and the phase difference between the first and second input terminals is calculated from the count values.

Abstract: A noise wave is received by a receiver and the received output is supplied to a first signal path composed of a rectifier and a low-pass filter connected to the output side thereof. The received output is applied to a second signal path comprised of an AC amplifier, or a rectifier for rectifying the amplified output, a low-pass filter for filtering the rectified output, and an attenuator for attenuating the filtered output. The outputs from the first and second signal paths are selectively provided to a time constant circuit by means of a switch in accordance with the received noise level. The input to the time constant circuit is converted into a quasi-peak value detected output, which is logarithmically amplified by a logarithmic amplifier and is then provided to an indicator.

Abstract: First and second frequency signals are frequency converted by a frequency converter and the frequency-converted output and the output from a variable frequency oscillating means are phase compared by a digital phase comparator. The phase-compared output controls the variable frequency oscillating means, constituting a first phase lock loop of a wide capture range. The output from the variable frequency oscillating means is frequency converted by the first frequency signal and the converted output and the second frequency signal are phase compared by an analog phase comparator. By the phase-compared output is controlled the variable frequency oscillating means, constituting a second phase lock loop of a narrow capture range but a large loop gain. The output frequency of the variable frequency oscillating means is varied by changing the setting of the frequencies of the first and second frequency signals.

Abstract: A plurality of resistance elements are connected via cutoff switches to form a ring. One of the connection points of each cutoff switch with the respective resistance element is connected via a feed switch to a common power source and via an output switch to a common output terminal. The other connection point of each cutoff switch with a resistance elements is connected via a grounding switch to a common potential point. An operation of turning OFF one of the cutoff switches, simultaneously turning ON the feed switch and the grounding switch on both sides of the turned-OFF cutoff switch, and turning ON the output switch selected in accordance with an input digital value, is repeated with a fixed period for all of the cutoff switches in a sequential order, while retaining the relative positions of the switches on the ring. By smoothing the output at the output terminal, scattered resistance values of the resistance elements are averaged.

Abstract: A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

Abstract: In a contact drive assembly for use with test equipment for testing, for example, an IC element, a movable contact piece is brought into contact with a terminal pin of the IC element to connect it to a measuring circuit. A flexible tube is disposed adjacent the movable contact piece and compressed air is supplied to the flexible tube to inflate it, biasing the movable contact piece to engage with or disengage from the terminal pin.

Abstract: A plurality of code signal generators are provided, respectively corresponding to bits of a digital signal to be converted. Each of the code signal generators generates a pulse signal having a duty ratio corresponding to the weight of the corresponding bit of the digital signal. The pulse signal is smoothed to provide a DC output corresponding to the weight of the bit. The outputs from the code signal generators corresponding to the respective bits of the input digital signal are summed by a summing circuit to obtain an analog converted output.

Abstract: The output from a reference voltage source is provided to a DC amplifier and its output is applied as a reference voltage to an output terminal. The output thus derived at the output terminal and the output from the reference voltage source are changed over by a switch to be alternately supplied to a smoothing circuit, the smoothed output from which is fed back to the DC amplifier. The switch is changed over periodically by a control signal from a control circuit, and by controlling the change-over ratio of the switch, a reference voltage of a desired value is provided at the output terminal. Thereafter, when the output voltage at the output terminal deviates from the reference value, the deviation is corrected by the feedback action.

Abstract: An analog input signal to be converted is subjected to first integration by an integrator and a reference signal opposite in polarity to the input analog signal is subjected to second integration by the integrator. After the integrator output has passed a predetermined level, a reference signal opposite in polarity to the abovesaid reference signal is subjected to third integration by the integrator for a predetermined period of time and then a reference signal of the same polarity as that in the second integration is subjected to fourth integration by the integrator at a rate of an integral fraction of the integration rate in the second integration. In the second integration, clock pulses are counted by a counter but the counting is interrupted for a period of time substantially twice as long as the third integration period and, in the fourth integration, the counting is performed at a counting stage of one lower order.

Abstract: The oscillation frequency of a variable frequency oscillator is swept by a sweep signal from a sweep signal generator and the oscillation frequency is compared with a preset sweep start frequency for detecting coincidence therebetween. Upon detecting the coincidence, the sweep operation of the sweep signal generator is stopped and, at the same time, the oscillation frequency of the variable frequency oscillator is made by phase lock loop means to be phase-synchronized with a reference frequency. When the phase synchronization is established, an error signal in the phase synchronization is held and the loop of the phase lock loop means is cut off and then the error signal is applied to the sweep signal generator to re-start the frequency sweep of the variable freqency oscillator. When coincidence is detected between the oscillation frequency of the variable frequency oscillator and a preset sweep stop frequency, the sweep operation is stopped.