Abstract: A plurality of metal resistance elements and a metal resistance element for compensation use are formed on a common substrate and placed under the same temperature condition. A reference current is applied to the metal resistance element for compensation use to yield an auxiliary reference voltage. A plurality of switches are individually connected in series to the reference metal resistance elements and the auxiliary reference voltage is provided to the series circuits to selectively control the switches, thereby obtaining various currents.

Abstract: A system for testing logical devices, in which a pattern file is used to store numerous test patterns, each of which includes both an input pattern, which is provided as an input to the device under test, and an expected value pattern, which is compared with the actual output of the device under test to ascertain whether malfunction has occurred. By accessing the pattern file at various addresses, different test patterns can selectively be applied to the device in a test. A command file includes instructions for controlling the sequence in which the various test patterns included in the pattern file are accessed, and an operand file includes data which may be required for carrying out the instructions contained in the command file. Index, stack point, and subroutine return registers are also used to execute the instructions which may be contained in the command file.

Abstract: A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.

Abstract: An input signal from an antenna is level-adjusted by a first level adjuster and then frequency-converted by a frequency converter. The frequency-converted signal is further level-adjusted by a second level adjuster and then detected by a detector, and the detected output is displayed on a first display. A control signal for controlling the frequency of a local oscillation signal of a local oscillator, which is applied to the frequency converter, is adjusted to select the input signal to be measured. The control signal is applied to a compensating signal generator to derive therefrom a compensating signal for compensating for the frequency characteristic of the antenna. The compensating signal, a first set signal representing the set value of the first level adjuster, and a second set signal representing the set value of the second level adjuster are added together.

Abstract: Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

Abstract: In an A-D converter of a dual slope system, a digital value set by setting means is provided to switch drive signal generating means to derive therefrom a switch drive signal of a time width corresponding to the digital value, and by the switch drive signal a switch is turned ON, through which a constant voltage is superimposed on an analog input voltage.

Abstract: A signal to be measured and a triangular signal are applied to a first mean square value circuit, in which they are added together, full-wave rectified and smoothed and, at the same time, the triangular signal and a measured output are provided to a second mean square value circuit, in which they are added together, full-wave rectified and smoothed. The outputs from the first and second mean square value circuits are subtracted one from the other in a subtractor to obtain the measured output, with the triangular signal component removed. The measured output is applied to the second mean square value circuit to derive therefrom as a measured output an effective value that the root mean square value of the signal to be measured have been extracted.

Abstract: A plurality of low-speed memories having stored therein a plurality of patterns and first and second high-speed memories of higher operating speed than the low-speed memories are provided. One of the first and second high-speed memories is read to obtain output patterns and, at the same time, the plurality of low-speed memories are simultaneously read and the read-out data are successively written in the other high-speed memory alternately with each other. Upon completion of pattern generation from the one high-speed memory, pattern generation from the other high-speed memory is achieved.

Abstract: The rise of an intermittently incoming pulse modulated wave is detected to open a gate circuit by the detected output to supply therethrough a clock pulse of a frequency higher than the carrier frequency of the incoming pulse modulated wave to a counter and a pulse decay detector for counting with the former and resetting the latter every carrier cycle of the pulse modulated wave. While the pulse modulated wave continue, the pulse decay detector is repeatedly reset to be prevented from overflowing. Upon interruption of the pulse modulated wave, the pulse decay detector overflows to provide an output after the elapse of predetermined time selected to be longer than one carrier cycle. By the overflow signal, the gate circuit is closed to stop the counting operation of the counter and the numerical value corresponding to the predetermined time is subtracted from the count value of the counter, thereby obtaining the pulse width of the pulse modulated wave.

Abstract: A digital frequency measuring device in which pulses of an input signal are counted for a certain period of time under the control of a gate signal and the count value is displayed in a digital form. A fraction detector circuit is provided for measuring the time interval or difference .DELTA.T.sub.1 between the leading edge of the gate signal and an input pulse arriving after it, the time interval or difference .DELTA.T.sub.2 between the trailing edge of the gate signal and an input pulse arriving after it and the unit period T of the input pulse signal, and performing an operation corresponding to (.DELTA.T.sub.1 - .DELTA.T.sub.2 /T. The result of operation is converted into the corresponding digital value, which is displayed as a fraction value of the abovesaid count value.

Abstract: Disclosed is an A-D converter in which a voltage to be measured is subjected to first integration for a certain period of time; a reference voltage of the opposite polarity from the voltage to be measured is subjected to second integration until the integrated value obtained by the first integration returns to a predetermined value; measuring clock pulses are counted by a counter circuit in the period of the second integration; and the voltage to be measured is converted by the count value of the counter circuit into a digital value. In the A-D converter, there are provided a variable frequency divider and a memory having stored therein frequency dividing ratio determining signals for changing the frequency dividing ratio of the variable frequency divider.

Abstract: A device for measuring the frequency or period of an input signal independent of different frequency noise signals which may be superimposed on the input signal includes a filter circuit having a variable cut-off frequency. The output level of the filter circuit is detected by a level detector, the output of which electrically controls a variable element such as a variable resistor, a variable capacitance diode or the like which is included in the filter circuit. This controls the cut-off frequency of the filter circuit, so as to maintain its output level at a given level. In this manner, an input signal frequency is converted into a corresponding level, utilizing a declining portion adjacent to the cut-off frequency of the frequency response of the filter circuit. The converted level is utilized to vary the cut-off frequency of the filter circuit to maintain its output level constant, thereby automatically changing the cut-off frequency in accordance with the input signal frequency.

Abstract: An input signal and a local oscillator signal are supplied to a harmonic mixer. The local oscillator signal is swept over a frequency range. The output from the harmonic mixer is supplied to an intermediate frequency filter having a preselected frequency response, which provides an output signal when the difference formed by subtracting one of the input signal frequency and one harmonic frequency of the local oscillator signal from the other is equal to the intermediate frequency or when the difference formed by subtracting the other frequency from said one frequency is equal to the intermediate frequency as the local oscillator frequency is swept. By choosing a time interval between the times when the pair of intermediate frequency output signals are obtained, the order of that harmonic of the local oscillator signal with which the intermediate frequency output signal is obtained is determined depending on the frequency of the input signal.