Abstract: A pair of substantially identical integrated circuit elements, in the form of microprocessors, are operated in response to the same instruction and data signals that are accessed from a memory by one of the integrated circuits. The accessed instruction and data signal are supplied, via a synchronous interface, to the second integrated circuit, which operates thinking that the supplied data and instruction signals were accessed by it in response to address and control signals. The states of the two integrated circuits are applied to comparator circuitry, both via buffered paths. The comparator circuitry is operated in response to control signals produced by the first integrated circuit to effect comparison on only those signals that are valid at any particular moment in time. Clock-synchronizing circuitry is included to ensure that predetermined state transitions of the clocks used to operate the first and second integrated circuit occur within a prescribed time period.

Abstract: A method and system for providing a fault tolerant access between network clients and a network server. Accordingly, a preferred embodiment of the present invention, a first primary input/output process (IOP) and a second backup IOP are provided in a first network client. A first backup IOP and a second primary IOP are provided in a second network client. The first backup IOP is a backup of the first primary IOP and the second backup IOP is a backup of the second primary IOP. A first preferred access path between the first primary IOP and the network server as well as a first alternate access path between the first backup IOP and the network server are defined. Similarly, a second preferred access path between the second primary IOP and the network server as well as a second alternate access path between the second backup IOP and the network server are defined. A first network connection between the first primary IOP and the network server is established via the first preferred access path.

Abstract: An apparatus and method for getting descriptors to data and passing the descriptors among data sources and sinks, thereby avoiding copying the data among the data sources and sinks. The data source/sink which consumes the data actual initiates the copying of the actual data itself, using global pointers to the data in the descriptors.

Abstract: A data structure representing an Interface Definition Language ("IDL") source file is disclosed. The data structure is preferably produced during the compilation of the source file and generation of language-specific source code. The data structure includes a variable-sized array of data structures representing entries from the source file in addition to an array of strings containing each line in the source file. Each of the entry data structures contains a fixed part containing information about the name and attributes of the source file entry and a variable part that depends upon the entry's data type. The data structure can be stored in a file or database for run-time access by distributed applications.

Abstract: An apparatus and method for getting descriptors to data and passing the descriptors among data sources and sinks, thereby avoiding copying the data among the data sources and sinks. The data source/sink which consumes the data actual initiates the copying of the actual data itself, using global pointers to the data in the descriptors.

Abstract: A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is created using the active edge of the first clock; first and second sampled patterns are generated by sampling the first pattern with respective first and second edges of the second clock; and a first acceptance signal is asserted if either the first or second sampled pattern has alternating binary one's and zero's. A second acceptance signal is asserted as above but interchanging the two clock signals. A near-frequency signal is generated when both acceptance signals are asserted. A clock error signal is the inversion of the near-frequency signal.

Abstract: Multiple processors are connected to form a multiprocessor system having interprocessor communicating capability. In the face of a power-fail signal, indicating that possible power loss is imminent, a processor will proceed through a shut-down procedure to save the present operating state so that when power is re-applied the processor can continue from the operating state it left when power was lost. The shut-down procedure concludes with the processor broadcasting messages to all other processors that it is undergoing a power-fail shut-down which is noted by the other processors to later cause them to enter a cautious mode of operation so as to not exclude the processor in any system configuration involving agreement of all processors by reason of the processor's loss of power.

Abstract: A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.

Abstract: A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.

Abstract: A multiprocessor system is configured so that each of the central processing units (CPUs) of the system have accessed at least portions of the memory of each other CPU. Interprocessor messaging is conducted by a CPU writing to, or reading from, the memory of another CPU of the system.

Abstract: A method and apparatus for detecting and tolerating situations in which one or more processors in a multi-processor system cannot participate in timer-driven or timer-triggered protocols or event sequences. The multi-processor system includes multiple processors each having a respective memory. These processors are coupled by an inter-processor communication network (preferably consisting of redundant paths).Processors are suspected of having failed (ceased operations) outright or having a failed timer mechanism when other processors detect the absence of periodic "IamAlive" messages from other processors. When this happens, all of the processors in the system are subjected to a series of stages in which they repeatedly broadcast their status and their connectivity to each other. During the first such stage, according to the present invention, a processor will not assert its ability to participate unless its timer mechanism is working.

Abstract: A system for dynamically graphically presenting a concept of interest related to the operation of a software target sub-system asks the sub-system to include changes in values relevant to the concept of interest in a telemetry stream propagated by the target sub-system. These values are held by receptors and collections of values relevant to the concept of interest are utilized to create renderings indicating characteristics of the concept of interest. A holder is provided for each value and a single value may be used to create different renderings thereby reducing the cost to the target sub-system. Whenever a value change is propagated each collection is notified so that the renderings are updated.

Abstract: An improved method and apparatus for creating a context-sensitive pathsend in a asynchronous data packet network of the kind used typically in on-line transaction processing where a particular receiving server in a server pool must communicate with a particular originating client. By piggybacking messages and employing run-time binding to create a logical connection between the server and client, the present invention achieves a dramatic improvement in processing data packets and minimizing system resources. In a preferred embodiment the invention is backwardly compatible with existing context-free applications.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

Abstract: Disclosed is method for aligning and mounting electrical components, such as packaged integrated circuits, to a printed circuit board. During an alignment phase, a sample component is attached to a stand-in circuit board at a component site. A base plate, having alignment elements, is then fitted to the board proximate the attached sample component. Next, a chuck is mounted to the sample component, and an alignment plate positioned to engage the alignment elements of the base plate, and affixed to the chuck, forming a chuck assembly that is aligned to the base plate and registered to the component site of the circuit board. During a production phase, the base plate is placed on a printed circuit board at a location substantially identical to that on the stand-in printed circuit board. A chuck assembly, configured substantially identical to that formed during the alignment phase, and carrying a component to be mounted, is attached to the base plate so that the alignment plate engages the alignment elements.

Abstract: An apparatus and protocol to determine the group of processors that will survive communications faults and/or timed-event failures in a multiprocessor system. The processors each have a respective memory, and the processors are coupled by means of an inter-processor communication network. The processors detect that the set of processors with which they can communicate has changed. They can choose to either halt or continue operations based on minimizing the likelihood that disconnected groups of processors will continue to operate as independent systems. The processors construct a connectivity matrix on the initiation of a regroup operation. The connectivity information is used to ensure that all the processors in the final group that survives can communicate with all other processors in the group. One or more processors may halt to achieve this characteristic.

Abstract: In a distributed network system, resilient virtual fault tolerant service sessions are conducted between a host application program and a telnet client user over an end-to-end link including a telnet server, a messaging protocol process, a network driver, and a communication link. The telnet server establishes a tty type structure in response to a service request from a telnet user/client. This invention includes a service control block which controls the establishment of a tty and associated request control blocks and buffers for processing I/O requests. The session is functionally partitioned into an upper half session involving the host application program and the telnet server, and a lower half session involving the remainder of the network components leading to the telnet client.

Abstract: A transaction checking system for improving the level of software fault tolerance in a distributed processing environment by aiding the client computer system in the recovery process. The transaction checker system enables the client computer system to determine, after a system failure, the state of the last transaction so that the client computer system can begin the recovery process.

Abstract: A method and apparatus for blind alignment of electronic circuit boards. A receptacle with two vertical flanges and one horizontal flange is positioned relative to an electrical connection. A circuit board having a notch on a leading edge is proximally positioned to the receptacle. As the notched edge is moved toward the receptacle, the flanges guide the board into a registered position relative to the electrical connection. The method and apparatus may be used in any number of alignment situations including those as disparate as robotic assembly operations and assembly by untrained consumers and end-users.