Patents Assigned to Tandem Computers
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Patent number: 5805920Abstract: A data processing system for transferring data is provided. This system includes central processing units (CPUs 20, 22, 24 and 26) and storage units (30 and 32 with 100-105 and 110-115) which are interconnected by a network (10). The CPUs (20, 22, 24 and 26) include a request process (133) and a storage process (130). The storage process (130) controls access to the storage unit (30 with 100-105 and 110-115). Software routines (220) are used to provide direct access to the storage unit (30 with 100-105 and 110-115) by the request CPU (22). The request CPU (20) is the CPU containing the request process (133). A virtual memory address for a buffer (160) of the request CPU (22) is created in the request CPU (22). The virtual memory address along with a storage unit access request are sent to the CPU (20) containing the storage process (130). A work request including the virtual memory address to sent from the storage process (130) to the storage unit (30 with 100-105 and 110-115).Type: GrantFiled: November 13, 1995Date of Patent: September 8, 1998Assignee: Tandem Computers IncorporatedInventors: Todd W. Sprenkle, Srinivasa D. Murthy, Anil Khatri
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Patent number: 5799323Abstract: A primary computer system has a database, application programs that modify the local database, and a transaction manager that stores audit records in a local audit trail reflecting those application program modifications to the local database. A plurality of parallel backup systems are used to provide "triple contingency protection" of the data on the primary computer system. However, if the primary system suffers a sudden catastrophic failure, the parallel backup systems will generally be left in inconsistent states. To restart the application programs on one of the backup system, the parallel backup are first synchronized with each other, and then transaction processing is restarted with one of the backup systems as the new primary system, and the other backup systems as the backups to the new primary system.Type: GrantFiled: January 30, 1997Date of Patent: August 25, 1998Assignee: Tandem Computers, Inc.Inventors: Malcolm Mosher, Jr., Gordon J. Bowring
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Patent number: 5799322Abstract: A primary computer system has a database, application programs that modify the local database, and a transaction manager that stores audit records in a local audit trail reflecting those application program modifications to the local database. A plurality of parallel backup systems are used to provide "triple contingency protection" of the data on the primary computer system. However, if the primary system suffers a sudden catastrophic failure, the parallel backup systems will generally be left in inconsistent states. To restart the application programs on one of the backup system, the parallel backup are first synchronized with each other, and then transaction processing is restarted with one of the backup systems as the new primary system, and the other backup systems as the backups to the new primary system.Type: GrantFiled: January 30, 1997Date of Patent: August 25, 1998Assignee: Tandem Computer, Inc.Inventor: Malcolm Mosher, Jr.
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Patent number: 5794252Abstract: A local computer system has local database, application programs that modify the local database, an a transaction manager that stores audit records in a local audit trail reflecting those application program modifications to the local database. A remotely located computer system has a backup database. A remote data duplication facility (RDF) is partially located in the local computer system and partially in the remote computer for maintaining virtual synchronization of the backup database with the local database. The RDF includes an extractor process executed by said local computer system, and a receiver process and a plurality of updater processes executed by the remote computer system. The extractor process extracts audit records from a local audit trail and transmits those records to the receiver process. The receiver process distributes the audit records into one or more image trail files that are associated with a particular updater process.Type: GrantFiled: December 16, 1996Date of Patent: August 11, 1998Assignee: Tandem Computers, Inc.Inventors: Bruce W. Bailey, Malcolm Mosher, Jr.
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Patent number: 5794034Abstract: An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.Type: GrantFiled: September 23, 1997Date of Patent: August 11, 1998Assignee: Tandem Computers IncorporatedInventors: Venkatesh Harinarayan, Srinivasa D. Murthy, Alan L. Rowe
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Patent number: 5790776Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.Type: GrantFiled: June 7, 1995Date of Patent: August 4, 1998Assignee: Tandem Computers IncorporatedInventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, John C. Krause, Kenneth H. Porter, William Joel Watson, Linda Ellen Zalzala
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Patent number: 5790868Abstract: A distributed computer system having a plurality of end user terminals and a plurality of loosely coupled server computers that share no resources with each other. A multiplicity of user application processes are distributed over the server computers. An Enq table is stored on a first one of the server computers. The Enq table includes Enq records, each representing a locked resource. When any user application process executes an Enq instruction naming a specific resource, if the Enq table does not already contain an Enq record for the specific resource an Enq record is generated and stored in the Enq table representing the specific resource as locked. The Enq record is stored in the same Enq table on the first server computer regardless of which server computer executes the Enq instruction. If the Enq table does already contain an Enq record for the specific resource, execution of the user application process that executed the Enq instruction is suspended.Type: GrantFiled: June 7, 1995Date of Patent: August 4, 1998Assignee: Tandem Computers, Inc.Inventors: Andreas E. Hotea, John S. de Roo, Mark Phillips
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Patent number: 5790807Abstract: An apparatus and method for getting descriptors to data and passing the descriptors among data sources and sinks, thereby avoiding copying the data among the data sources and sinks. The data source/sink which consumes the data actual initiates the copying of the actual data itself, using global pointers to the data in the descriptors.Type: GrantFiled: December 20, 1995Date of Patent: August 4, 1998Assignee: Tandem Computers IncorporatedInventors: Leonard R. Fishler, Bahman Zargham
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Patent number: 5785397Abstract: An effective connector mechanism is described which allows modules (10, 12) to be easily and reliably connected and disconnected. This connector mechanism includes a coordinated arrangement of guide plates (28, 54) featuring mating guide rails (56) and U-shaped channels (32) along with matched sets of tapered pins (38, 40) with tapered slots (58, 59). The pins and slots are "tapered" in the sense that the pins have a slanted surface (52) on the shank (44) directly underneath the head (42) which urges the guide plate surface adjoining the slot downward after engagement and the slots have a slanted edge (66) at their closed end (62) which maintains contact with the pin after engagement. When mated together, the rails, U-shaped channels, pins and slots lock the modules into engagement in virtually every direction.Type: GrantFiled: December 21, 1995Date of Patent: July 28, 1998Assignee: Tandem Computers IncorporatedInventor: John Pavelski
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Patent number: 5778171Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.Type: GrantFiled: April 21, 1995Date of Patent: July 7, 1998Assignee: Tandem Computers IncorporatedInventors: Mizanur Mohammed Rahman, Fred C. Sabernick, Jeff A. Sprouse, Martin Jiri Grosz, Peter Fu, Russell Mark Rector
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Patent number: 5778354Abstract: A database management system (DBMS) provided with a multi-dimensional improved indexed accessing capability using keyed index searching. Individual search keys are constructed from general expression statements created in the DBMS compiler from search queries supplied to the DBMS. Each key column represents another dimension, and both ranges and IN lists can be specified in the search query and used as the predicate values in multiple columns. Missing predicate values in the search query are interpreted as a specification of the minimum and maximum values for the associated search key column. During compile time, the DBMS compiler produces general expressions to be used by the DBMS executor during run time to create the search keys. The DBMS compiler evaluates search queries by associating predicates with clusters and disjunct numbers assigned to each individual disjunct in the search query expression.Type: GrantFiled: June 7, 1995Date of Patent: July 7, 1998Assignee: Tandem Computers IncorporatedInventors: Harry A. Leslie, David W. Birdsall, Rohit N. Jain, Hedieh Yaghmai
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Patent number: 5774640Abstract: A fault tolerant network interface is achieved by providing primary and alternate network controllers, dual transceivers, dual cables and dual connectors. This fault tolerant interface is driven by a logical device driver which controls the physical device drivers for the primary and alternate network controllers. The logical device driver causes periodically polling messages to be sent between the primary and alternate network controllers to determine if a fault has occurred in either of these network controllers. Faults detected are logged and error recovery actions are provided according to the nature of the faults detected. If the primary network controller is found to be faulty, the secondary network controller will assume the physical address of the primary network controller and provides the services of the primary network controller while the primary network controller is effectively removed from the network.Type: GrantFiled: October 21, 1991Date of Patent: June 30, 1998Assignee: Tandem Computers IncorporatedInventor: Kay M. Kurio
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Patent number: 5771344Abstract: First and second data processing systems located at first and second sites are configured with the first data processing system having a primary memory unit at the first site and a mirror memory unit at the second site with the first and second sites coupled by a single-mode optical fiber. Fiber optic switches at the first and second sites can be reconfigured to coupled the mirror disc to the second data processing system with minimal delay.Type: GrantFiled: September 9, 1996Date of Patent: June 23, 1998Assignee: Tandem Computers IncorporatedInventors: Wing Ming Chan, Wouter Senf, Timothy C. K. Chou, Mark H. Roettgering, Nusret Yurutucu, Craig F. Adams
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Patent number: 5768564Abstract: A method, system, apparatus, and program for translating one computer language to another using doubly-rooted tree data structures. A doubly-rooted tree is the combination of two sets of hierarchically related objects sharing a common set of leaves. An N-rooted tree is also described. When a doubly-rooted tree is constructed in the specified manner and then translated to a second doubly-rooted tree, source language code is transformed into target language code. In addition, the translation preserves preprocessor characteristics of the source language code including macros, conditionally compiled regions of code, source inclusion statements, and comments.Type: GrantFiled: October 7, 1994Date of Patent: June 16, 1998Assignee: Tandem Computers IncorporatedInventors: Kristy A. Andrews, Paul Del Vigna, Mark E. Molloy
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Patent number: 5765007Abstract: First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. This allows simultaneous accessing of different microinstructions using a single address incrementer. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines.Type: GrantFiled: November 13, 1992Date of Patent: June 9, 1998Assignee: Tandem Computers IncorporatedInventors: Mizanur M. Rahman, Robert W. Horst, Richard Harris
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Patent number: 5764879Abstract: A fault tolerant computer system distributes audit trail files containing audit records, across an arbitrary number of disk volumes. After one audit trail file becomes full, audit records are directed toward a next audit trail file stored on a different disk volume. Storage of newly generated audit rotates through the disk volumes in roundrobin fashion. Full audit trail files are eventually archived and their space becomes available again for renaming and storage of newly generated audit records. The number of audit records available for on-line recovery after a failure is not limited to the storage capacity of any single disk volume. Furthermore, there is no contention for disk access between archiving of full audit trail files and storage of newly generated audit records.Type: GrantFiled: July 29, 1996Date of Patent: June 9, 1998Assignee: Tandem Computers, Inc.Inventors: Michael J. Skarpelos, Robert van der Linden, William J. Carley, James A. Lyon, Matthew C. McCline
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Patent number: 5758113Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.Type: GrantFiled: March 10, 1997Date of Patent: May 26, 1998Assignee: Tandem Computers IncorporatedInventors: Charles E. Peet, Jr., John David Allison, Kenneth C. Debacker, Robert W. Horst
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Patent number: 5757918Abstract: A new process is described for verifying a user and/or authenticating a smart card in an off-line computer environment with limited a priori knowledge on the part of the verifier. This process advantageously uses the computational capability and the physical and logical security characteristics offered by a smart card.Type: GrantFiled: September 30, 1996Date of Patent: May 26, 1998Assignee: Tandem Computers IncorporatedInventor: W. Dale Hopkins
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Patent number: 5754752Abstract: A session recovery mechanism that permits the recovery of a session with a minimal delay to a user and with minimal data loss. When the client/server communications protocol process, such as TCP/IP process, issues an error message to a server and a client, the server and the client switch from a server data socket and a client data socket, respectively, to a new server data socket and a new client data socket, respectively. This switchover is achieved by having the client open a listening socket during its initialization process. Using the client listening socket, the client listens for a connection from the server to switch to a new data socket, in case of, for example, error messages from the TCP/IP process.Type: GrantFiled: March 28, 1996Date of Patent: May 19, 1998Assignee: Tandem Computers IncorporatedInventors: Yi-Ren Peter Sheh, Roger James Schroeder
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Patent number: H1741Abstract: A method and apparatus for stress testing a computer memory system is disclosed. A sequential series of bit patterns, comprising 1's and 0's, is impressedd upon a computer memory so that, during testing, every memory cell stores a 1 while the eight adjacent neighboring memory cell stores 0's. Subsequently, the complimentary bit patterns are impressed upon memory, wherein every memory cell, at some time during the test, stores a 0 while the eight immediately adjacent neighboring memory cells store 1's. The disclosed bit pattern maximizes stress on the cells, In an interleaved dual memory bank configuration, memory cells are sequentially accessed from the highest to the lowest address of one memory bank, while memory cells are sequentially accessed from the lowest to the highest memory address in the other memory bank. Toggling successive memory accesses between the dual interleaved memory banks maximizes stress on the address driver components of the computer memory system.Type: GrantFiled: December 5, 1994Date of Patent: July 7, 1998Assignee: Tandem Computers CorporationInventor: Melvin Lee Cruts