Abstract: A sensor device may include a base layer, and an ASIC element disposed on the base layer. The ASIC element may include a plurality of electrical contact points. The sensor device may include a MEMS element. The MEMS element may include a plurality of through-silicon vias. The sensor device may include a plurality of conductive contact elements. Each conductive contact element may be disposed between, and electrically coupling, a respective through-silicon via and a respective electrical contact point. The sensor device may include a protective layer disposed between the ASIC element and the MEMS element. The protective layer may be composed of material(s) having a physical property defined to permit the protective layer to mitigate stress forces directed from the ASIC element to the MEMS element, to prevent corrosion, and/or to prevent leakage current between electrical connections due to pollution and/or humidity.

Abstract: A device for excitation of a resolver comprising an excitation coil and one or more sensing coils includes circuitry. The circuitry is configured to amplify a carrier signal using a first gain value to generate an excitation signal for output to the excitation coil of the resolver and determine whether the excitation signal is outside of a threshold band of voltages. The circuitry is further configured to amplify the carrier signal using a second gain value, wherein the second gain value is generated based on whether the excitation signal is outside of the threshold band of voltages.

Abstract: A time-of-flight (ToF) image sensor system includes a pixel array, where each pixel of the pixel array is configured to receive a reflected modulated light signal and to demodulate the reflected modulated light signal to generate an electrical signal; a plurality of analog-to-digital converters (ADCs), where each ADC is coupled to at least one assigned pixel of the pixel array and is configured to convert a corresponding electrical signal generated by the at least one assigned pixel into an actual pixel value; and a binning circuit coupled to the plurality of ADCs and configured to generate at least one interpolated pixel, where the binning circuit is configured to generate each of the at least one interpolated pixel based on actual pixel values corresponding to a different pair of adjacent pixels of the pixel array, each of the at least one interpolated pixel having a virtual pixel value.

Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

Abstract: A power semiconductor diode includes a semiconductor body having first and second main surfaces opposite to each other along a vertical direction. A drift region of a second conductivity type is arranged between an anode region of a first conductivity type and the second main surface. A field stop region of the second conductivity type is arranged between the drift region and the second main surface. A dopant concentration profile of the field stop region along the vertical direction includes a maximum peak. An injection region of the first conductivity type is arranged between the field stop region and the second main surface, with a pn-junction between the injection and field stop regions. A cathode contact region of the second conductivity type is arranged between the field stop region and the second main surface. A first vertical distance between the pn-junction and the maximum peak ranges from 200 nm to 1500 nm.

Abstract: A circuit for controlling a switch of a power converter includes a first clock signal generator configured to generate a first clock signal and a switching signal generator configured to generate a switching signal to control the switch of the power converter based on the first clock signal. The circuit further includes error detection circuitry configured to output an error indication and a second clock signal generator configured to generate, in response to the error indication, a second clock signal that comprises an edge of a clock cycle of the second clock signal that corresponds to when the switching signal deactivates the switch of the power converter plus a time delay. The switching signal generator is configured to generate the switching signal to control the switch of the power converter further based on the second clock signal in response to the error indication being output by the error detection circuitry.

Abstract: A belt tensioner for an engine accessory drive is installed over a pulley such that rollers extend toward the engine. Due the belt being between the tensioner and the engine, installation of the belt on the pulley is difficult. To simplify installation, a removable belt guide is included in the belt tensioner. Two methods of installing the belt and tensioner are envisioned. In a first method, the belt is first installed on the pulley and the belt guide holds the belt toward the pulley radially as the tensioner is installed over the pulley. In a second method, the belt is first installed to the tensioner and the guide holds the belt radially away from the pulley as the tensioner is installed over the pulley. In both methods, the belt guide is removed after the belt and tensioner are installed.

Abstract: A radar system is provided that includes a radar monolithic microwave integrated circuit (MMIC). The radar MMIC includes a plurality of radar signal channels; and at least one sensor configured to measure a physical parameter related to a temperature of the radar MMIC, and to generate sensor data corresponding to measured values of the physical parameter; and a controller configured to receive the sensor data from the at least one sensor, and to determine a channel operation of the plurality of radar signal channels, including selectively disabling at least a first radar signal channel of the plurality of radar signal channels and selectively enabling at least a second radar signal channel of the plurality of radar signal channels based on the measured values.

Abstract: A device for connecting a first network comprising a first energy storage element and a second network comprising a second energy storage element includes switching circuitry and pre-charging circuitry. The switching circuitry is configured to electrically couple the first network and the second network. The switching circuitry comprises a first switching element configured to bi-directionally allow current between the first network and a center point node when operating in a closed state. The switching circuitry further comprises a second switching element configured to bi-directionally allow current between the second network and the center point node when operating in a closed state. The pre-charging circuitry is configured to limit current to the center point node when a first voltage at the first energy storage element equalizes with a second voltage at the second energy storage element.

Abstract: A driver circuit is configured to deliver drive signals from an output pin to a power switch to control ON/OFF switching of the power switch. A first detection pin of the driver circuit is configured to receive a first signal associated with the power switch, wherein the first signal indicates a voltage drop over the power switch and a voltage drop over one or more other circuit elements. A second detection pin is configured to receive a second signal, wherein the second signal indicates a voltage drop over one or more matched circuit elements, wherein the one or more matched circuit elements associated with the second signal are substantially identical to the one or more other circuit elements associated with the first signal. The driver circuit is configured to determine the voltage drop over the power switch based on a difference between the first signal and the second signal.

Abstract: A novel concept for Near Field Communication (NFC) is described herein. In accordance with the embodiments described herein, orthogonal carrier signals are transmitted between NFC transmitter and NFC receiver circuit. In one arrangement, a carrier signal is unmodulated to ensure uninterrupted energy transfer to the receiver circuit. The orthogonal carriers are used to implement full-duplex Near Field Communication.

Abstract: A relay arrangement includes at least two series-connected relays, which are mechanically and electrically connected to a main printed circuit board via first terminals and second terminals, and at least one flat conductor for conducting current between the at least two series connected relays. The flat conductor is mechanically connected to the main printed circuit board and electrically and thermally connected to the first terminals of the relays, and the at least one flat conductor is configured to dissipate heat produced during operation of the relays.

Abstract: A method of detecting a serial arc fault in a DC-power circuit includes injecting an RF-signal with a narrow band-width into the DC-power circuit and measuring a response signal related to the injected RF-signal in the DC-power circuit. The method further includes determining a time derivative of the response signal, analyzing the time derivative, and signaling an occurrence of a serial arc fault in the power circuit based on the results of the analysis. A system for detecting an arc fault is configured to perform a method as described before.

Abstract: A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

Abstract: A method for calibrating a radar system includes generating an RF oscillator signal and distributing the RF oscillator signal to a plurality of phase shifters each providing a respective phase-shifted RF oscillator signal; receiving the phase-shifted RF oscillator signals by corresponding radar chips and radiating the phase-shifted RF oscillator signal via a first RF output channel of a first one of the radar chips; receiving a back-scattered signal by at least one RF input channel of each radar chip and generating a plurality of base-band signals by down-converting the received signals into a base band using the phase-shifted RF oscillator signals received by the corresponding radar chips; determining a phase for each base-band signal; and adjusting the phase shifts caused by the phase shifters such that the phases of the base-band signals match a predefined phase-over-antenna-position characteristic.

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Abstract: An electronic fuse circuit includes an electronic switch with a load current path coupled between an output node and a supply node and that connects or disconnects the output node and the supply node in accordance with a drive signal. The circuit includes a control circuit to generate the drive signal based on an input signal. A monitoring circuit is included in the control circuit to receive a current sense signal representing the load current passing through the load current path and to determine a first protection signal based on the current sense signal and a wire parameter. The first protection signal is indicative of whether to disconnect the output node from supply node. The control circuit changes from normal mode to idle mode when the load current is below a given current threshold and another criterion is fulfilled.

Abstract: A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

Abstract: An apparatus for generating magnetic vortex spin structures includes a device for moving at least one magnetic domain wall in a magnetic domain wall channel structure; and a device for generating and storing at least one magnetic vortex spin structure in response to the magnetic domain wall moved in the domain wall channel structure.

Abstract: A cage for a bearing, including: a first annular segment; a second annular segment located radially inwardly of the first annular segment; a vane connected to the first annular segment and to the second annular segment and including a first axial end facing at least partly in a first axial direction parallel to an axis of rotation of the cage and a second axial end facing at least partly in a second axial direction, opposite the first axial direction, the second axial end off-set from the first axial end in a circumferential direction around the axis of rotation; and a curved surface connected to the first annular segment and the second annular segment and arranged to retain a ball of the bearing. The first annular segment, the second annular segment, the vane, and the curved segment define a channel passing through the cage.