Abstract: An image acquisition method includes storing a coefficient of a relational expression between a parameter corresponding to a light quantity incident on an imaging sensor including a photo sensor element and an output value of the imaging sensor in the case of the light incident on the imaging sensor which employs a reference image accumulation time, inputting a desired image accumulation time, and calculating a parameter for obtaining a desired output value of the imaging sensor by using a corrected relational expression obtained by correcting using an output value of the imaging sensor employing the desired image accumulation time in the case of the incident light quantity being zero, adjusting the light quantity incident on the imaging sensor to be a calculated parameter, and acquiring a target image by the imaging sensor on which an adjusted light quantity is incident, and outputting data of the acquired image.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions.

Abstract: An image sensor has a plurality of pixels arranged in a row direction and in a column direction. Each pixel comprises a color filter that has a portion with a low transmissivity and a portion with a high transmissivity, and a photoelectric conversion element that includes a first photoelectric conversion cell which receives light transmitting through the portion with the low transmissivity of the color filter, and a second photoelectric conversion cell which receives light transmitting through the portion with the high transmissivity of the color filter. The plurality of pixels are arranged such that positions of the portions with the low transmissivity for pixels of one color are identical among the plurality of pixels, and the portions with the low transmissivity are positioned adjacent to each other between adjacent pixels of different colors in the row direction only.

Abstract: Methods and systems for reducing noise in homomorphic multiplication include: receiving a plurality of ciphertexts, each having a corresponding level; receiving data specifying a homomorphic multiplication on two ciphertexts; for two ciphertexts having different levels: adjusting a scaling factor of a first ciphertext so that the respective scaling factors of the two ciphertexts are the same; performing the homomorphic multiplication; and rescaling a result of the homomorphic multiplication; for two ciphertexts having the same level: performing the homomorphic multiplication; rescaling a result of the homomorphic multiplication; and using the scaling factors of the two ciphertexts during a decryption process.

Abstract: A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.

Abstract: A permanent magnet rotor structure for an underwater motor, an underwater motor and underwater equipment, related to the field of motors. The permanent magnet rotor structure for the underwater motor includes a rotor end cover; a plurality of permanent magnets arranged on an inner circumferential surface of the rotor end cover; a protective attachment structure arranged on surfaces of the plurality of permanent magnets; and an adhesive layer for adhering the protective attachment structure to the surfaces of the plurality of permanent magnets and covering the protective attachment structure. The permanent magnet rotor structure has characteristics of corrosion resistance and wear resistance, so that the service life of the underwater motor comprising the permanent magnet rotor structure can be prolonged.

Abstract: A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.

Abstract: A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

Abstract: A comparator includes a first-stage circuit, a second-stage circuit, a first switching circuit and a second switching circuit. The first-stage circuit includes a first input circuit and a second input circuit. The first switching circuit is configured to control the conduction of the first input circuit, and the second switching circuit is configured to control the conduction of the second input circuit. The first input circuit is configured to generate a first differential signal in a sampling phase when being switched on. The second input circuit is configured to generate a second differential signal in a sampling phase when being switched on. The second-stage circuit is configured to amplify and latch the first differential signal or the second differential signal in a regeneration phase to output a comparison signal.

Abstract: A method for preparing a tooth crown may include generating a 3D model of an external surface of a patient's tooth and generating a 3D model of an external surface of a first crown based on the 3D model of the external surface of the patient's tooth. The method may also include preparing the patient's tooth to receive the first crown while generating the 3D model of the external surface. A 3D model of the prepared tooth my be generated. A 3D model of an internal surface of the first crown may also be generated. The 3D model of the external surface and the 3D model of the internal surface may form a 3D model of the first crown.

Abstract: A messaging channel is embedded directly into a media stream. Messages delivered via the embedded messaging channel are extracted at a client media player. According to a variant embodiment, and in lieu of embedding all of the message data in the media stream, only a coordination index is injected, and the message data is sent separately and merged into the media stream downstream (at the client media player) based on the coordination index. In one example embodiment, multiple data streams (each potentially with different content intended for a particular “type” or class of user) are transmitted alongside the video stream in which the coordination index (e.g., a sequence number) has been injected into a video frame. Based on a user's service level, a particular one of the multiple data streams is released when the sequence number appears in the video frame, and the data in that stream is associated with the media.

Abstract: Some embodiments include an integrated assembly having first and second pillars of semiconductor material laterally offset from one another. The pillars have source/drain regions and channel regions vertically offset from the source/drain regions. Gating structures pass across the channel regions, and extend along a first direction. An insulative structure is over regions of the first and second pillars, and extends along a second direction which is crosses the first direction. Bottom electrodes are coupled with the source/drain regions. Leaker-device-structures extend upwardly from the bottom electrodes. Ferroelectric-insulative-material is laterally adjacent to the leaker-device-structures and over the regions of the bottom electrodes. Top-electrode-material is over the ferroelectric-insulative-material and is directly against the leaker-device-structures. Some embodiments include methods of forming integrated assemblies.

Abstract: Various embodiments include methods and systems having detection apparatus operable to cancel or reduce leakage signal originating from a source signal being generated and transmitted from a transmitter. A leakage cancellation signal can be generated digitally, converted to an analog signal, and then subtracted in the analog domain from a received signal to provide a leakage-reduced signal for use in detection and analysis of objects. A digital cancellation signal may be generated by generating a cancellation signal in the frequency domain and converting it to the time domain. Optionally, an estimate of a residual leakage signal can be generated and applied to reduce residual leakage remaining in the leakage-reduced signal. Additional apparatus, systems, and methods can be implemented in a variety of applications.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.

Abstract: A high reliability drug infusion device, includes: a drug storage unit including a drug outlet; a screw connected to a piston and a driving wheel provided with wheel teeth, respectively, the driving wheel drives the screw to move by rotation, pushing the piston forward; at least one driving unit cooperating with the driving wheel, the driving unit includes at least one driving portion a power unit and a reset unit connected to the driving unit, and the reset unit includes an elastic reset component and a linear-actuated reset component, and the elastic reset component alone applies a force to or together with the linear-actuated reset component to control the reset movement of the driving unit. The high reliability drug infusion can be used for improving the reliability and increasing the user's flexibility in choosing the infusion method.

Abstract: An input sampling method includes the following: acquiring a first pulse signal and a second pulse signal respectively; widening a pulse width of the first pulse signal to obtain a widened first pulse signal; shielding an invalid signal in the second pulse signal based on the widened first pulse signal to obtain a to-be-sampled signal; and finally, sampling the to-be-sampled signal based on a clock signal. In this way, prior to signal sampling, the invalid signal is shielded to avoid additional power consumption caused by sampling the invalid signal, and at the same time, the pulse width of the signal is widened to avoid sampling failure.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base having first contact layers and a second contact layer; forming an initial electrical connection layer; forming a lower mask layer including a first and a second pattern regions, and on an upper surface of the base, orthographic projections of two first contact layers fall within an orthographic projection of one first pattern region, and an orthographic projection of one second contact layer falls within an orthographic projection of one second pattern region; patterning the first pattern region to form two first sub-pattern regions discrete from each other; and etching the initial electrical connection layer to form first electrical connection layers and a second electrical connection layer discrete from each other, in which the first electrical connection layers correspond to the first sub-pattern regions, and the second electrical connection layer corresponds to the second pattern region.

Abstract: Disclosed herein is an apparatus that includes a plurality of cell capacitors arranged in a memory cell array region of a semiconductor substrate, each of the plurality of cell capacitors having a first electrode, a second electrode and an insulating film therebetween to electrically disconnect the first and second electrodes, a first conductive member including the plurality of cell capacitors therein, the first conductive member being electrically connected in common to the first electrodes of the plurality of cell capacitors, and a second conductive member formed on an upper surface of the first conductive member, a material of the second conductive member being different from that of the first conductive member. A side surface of the first conductive member is free from the second conductive member.

Abstract: A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.