Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Abstract: Systems and methods for gesture-based control are disclosed. In some embodiments, a system may include a wearable device configured to obtain physiological data and wrist location data. The system may be configured to detect a first gesture and transition to an object control state in which changes in the wrist location data and/or the physiological data are configured to control a movement of the object. In the object control state, the system may be configured to detect a first motion of a body part, generate a first command to move the object in a first command direction, detect a second motion of the body part, and generate a command to move the object in a second command direction. The system may detect a second gesture indicating an intention to cease control of the object, and transition out of the object control state.

Abstract: A semiconductor structure includes a Through Silicon Via (TSV) and a protective ring disposed outside the TSV; the protective ring includes at least two protective layers arranged in parallel and surrounding the TSV; each of the protective layers includes a first protective structure and second protective structures disposed surrounding the first protective structure; the first protective structure is a polygonal structure; a number of sides of the polygonal structure is greater than or equal to 4; and the second protective structures are disposed on an inner side and an outer side of each corner area of the polygonal structure.

Abstract: A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.

Abstract: An input sampling method includes the following operations. A first pulse signal and a second pulse signal are received. Logical operation is performed on the first pulse signal and the second pulse signal to determine a to-be-sampled signal. The to-be-sampled signal is obtained by shielding an invalid part of the second pulse signal according to a logical operation result. Sampling process is performed on the to-be-sampled signal to obtain a target sampled signal.

Abstract: A memory includes a plurality of semiconductor structures stacked onto one another. Each of the plurality of semiconductor structures include: a first base including a peripheral circuit structure; a first integrated circuit layer disposed on the first base and electrically connected to the peripheral circuit structure; and a second base disposed on the first integrated circuit layer. A first dielectric layer is disposed between the first integrated circuit layer and the second base. The second base includes a storage circuit structure. Each of the first base and the second base includes a semiconductor layer.

Abstract: A method for manufacturing a semiconductor device includes: forming an isolating layer on a surface of a substrate; forming a groove on the isolating layer, where the groove penetrates the isolating layer; forming a protection layer in the groove and on the isolating layer; forming a dielectric layer on the protection layer; and forming a contact hole, where the contact hole penetrates the protection layer and the dielectric layer to the surface of the substrate, respectively. The method for manufacturing the semiconductor device according to the present invention can be used not only in chemical vapor deposition but also in a process of a metal wire of a short-circuit in physical vapor deposition.

Abstract: A planar inductor may include a first coil and a second coil. The first coil may include a first trace that forms a first set of turns. The second coil may include a second trace that forms a second set of turns. A distance between the turns of the first set of turns may be equal to a distance between the turns of the second set of turns. A width of the first trace may be equal to a width of the second trace. The first coil and the second coil may be physically positioned or sized according to a/b in which a represents the width of the first trace and b represents the distance between the turns of the first set of turns.

Abstract: Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.

Abstract: A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.

Abstract: An internal combustion engine operates so that it delivers zero or negative torque. The engine operates in either a deceleration cylinder cut off (DCCO) mode or skip cylinder compression braking mode. In the skip cylinder compression braking mode, selected working cycles of selected working chambers are operated in a compression release braking mode. Accordingly, individual working chambers are sometimes not fired and sometimes operated in the compression release braking mode while the engine is operating in the skip cylinder compression braking mode.

Abstract: Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Abstract: An apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.

Abstract: A network controller is configured to cause a network to implement a primary network configuration of a network and a secondary network configuration as a backup to the primary network configuration. The network controller may be configured to receive information from a plurality of nodes of a network and information related to the client data to be transmitted through the network. Based on the node information, the network controller is configured to determine available nodes and possible links in the network and then determine a topology of the network. The primary network configuration is determined based on the topology. The network controller then sends instructions to the plurality of nodes of the network to implement the primary network configuration and to switch to a secondary network configuration where a failure of the primary network configuration occurs, wherein the secondary network configuration implements mobile ad-hoc networking in the determined topology.

Abstract: A device includes a memory array with first memory cell and second memory cell, and control logic, operatively coupled with the memory array, to cause a first threshold voltage (Vt) state read out of the first memory cell to be converted to a first integer value and a second Vt state read out of the second memory cell to be converted to a second integer value; translate a combination of the first integer value and the second integer value to a set of three logical bits; and output, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first Vt state and a third set of logical bits corresponding to the second Vt state.

Abstract: A computing platform configured to (i) cause a client station to display, via a graphic user interface (“GUI”), a set of line items and a set of given attribute values that may be bulk associated with the line items, (ii) receive, from the client station, a request to activate a bulk association mode for bulk associating the line items with a given attribute value, (iii) cause the client station to display, via the GUI, a bulk association view indicating that the bulk association mode has been activated, the bulk association view comprising a target region for receiving user input comprising a selection of the line items to be bulk associated with the given attribute value, (iv) receive, from the client station, an indication that the user input has been received, and (v) based on the user input, update each respective line item with the given attribute value.

Abstract: A refrigeration or climate-control system may include a housing, an evaporator, a drain pan, and a fan. The evaporator may be disposed within the housing and may include a coil positioned in a horizontal orientation. The drain pan may be disposed within the housing and may include an inclined lower wall disposed vertically beneath the coil. The lower wall may define an airflow path underneath the coil. The fan may force the air through the housing and airflow path.

Abstract: Implementations for providing communication services using a virtual environment are described. An audio communication session may be established between a first user device and a second user device. The second user device may answer the audio communication session using a virtual environment. The virtual environment may be updated to display virtual features associated with the communication session.

Abstract: Memory devices and methods of operating memory devices in which maintenance operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., operations in excess of a predetermined threshold) warrants a maintenance operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of operations at the memory location, to schedule a maintenance operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled maintenance operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further operations at the memory location until after the count has been decreased.

Abstract: A transcription service may receive a request from a developer to build a custom speech-to-text model for a specific domain of speech. The custom speech-to-text model for the specific domain may replace a general speech-to-text model or add to a set of one or more speech-to-text models available for transcribing speech. The transcription service may receive a training data and instructions representing tasks. The transcription service may determine respective schedules for executing the instructions based at least in part on dependencies between the tasks. The transcription service may execute the instructions according to the respective schedules to train a speech-to-text model for a specific domain using the training data set. The transcription service may deploy the trained speech-to-text model as part of a network-accessible service for an end user to convert audio in the specific domain into texts.