Abstract: The disclosure relates to the technical field of semiconductors, and to a memory, a semiconductor structure and a method for same. The method includes: providing a substrate, the substrate including a plurality of conductive contact plugs in array distribution and insulation layers separating the conductive contact plugs; and forming a plurality of capacitive layers stacked and distributed in a direction perpendicular to the substrate on a surface of the substrate, each of the capacitive layers including a plurality of capacitances distributed at intervals, and the capacitances being respectively connected to different conductive contact plugs. According to the method, the storage capacity of capacitances can be increased, and product yield can be enhanced.

Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

Abstract: A semiconductor structure is provided. The semiconductor structure includes: a substrate and an active pillar located above the substrate. The active pillar extends in a first direction. The first direction is parallel to a plane where the substrate is located. The active pillar includes a body area extending in the first direction and a peripheral area surrounding the body area. The peripheral area includes a channel area. A type of doped ions of the channel area is the same as a type of doped ions of the body area, and a doping concentration of the channel area is greater than a doping concentration of the body area.

Abstract: An anti-fuse structure includes: a first unit including a first selection transistor, a first anti-fuse (AF) cell and a second AF cell; and a second unit including a second selection transistor, a third AF cell and a fourth AF cell. The first unit and second unit share an active region, which is provided with a first extension part and a second extension part which are independent of each other at a first side, and provided with a third extension part and a fourth extension part which are independent of each other at a second side, the first side being opposite to the second side. The first AF cell is arranged at the first extension part, the second AF cell is arranged at the second extension part, the third AF cell is arranged at the third extension part, and the fourth AF cell is arranged at the fourth extension part.

Abstract: A signal sampling circuit includes: a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a clock processing circuit, configured to perform two-stage sampling and logical operation on the to-be-processed chip select signal according to a first clock signal to obtain a chip select clock signal; a chip select control circuit, configured to perform sampling on the to-be-processed chip select signal according to the first clock signal to obtain an intermediate chip select signal, and perform logical operations on the intermediate chip select signal, the to-be-processed chip select signal and the to-be-processed command signal to obtain a command decoding signal; and an output sampling circuit, configured to perform sampling on the command decoding signal according to the chip select clock signal to obtain a target command signal.

Abstract: Vehicle occupant anomaly detection is provided. A system can receive sensor data from sensors associated with a vehicle, the sensors including an imaging sensor and the sensor data including 3D point representations of a vehicle occupant. The system can extract a time-series features of the vehicle occupant from the 3D point representations. The system can execute a machine learning model using the time-series features to determine at least one condition of the vehicle occupant. The system can, responsive to the condition, generate an instruction to cause the vehicle to perform a navigational action.

Abstract: The invention relates to a hemostatic composition in powder form comprising collagen of the fibrillar type comprising a content of fibrous collagen and/or fibrillar collagen of at least 70% by weight relative to the total weight of the collagen, and at least one monosaccharide, and optionally, at least one compound selected from coagulation factors and glycosaminoglycans. The invention further relates to a method for preparing such composition, and to a unit comprising such composition and a spraying device.

Abstract: A semiconductor structure is formed by: providing a substrate, wherein an insulation layer, an initial metal conductive layer, an initial sacrifice layer, and a mask layer stacking in sequence are formed on the substrate, wherein the initial sacrifice layer includes a metal oxide layer; forming a metal conductive layer and a sacrifice layer atop the metal conductive layer by etching the initial sacrifice layer and the initial metal conductive layer using an oxygen source gas as an etching gas based on a patterned mask layer; removing the patterned mask layer by performing an ashing process using the oxygen source gas as the etching gas; removing the sacrifice layer as well as a by-product formed during the etching and the ashing process and exposing the metal conductive layer by performing a corrosion process using an alkaline corrosion solution; and forming an isolation structure between adjacent metal conductive layers.

Abstract: A transistor includes: a substrate including an active area; a gate structure penetrating through the active area and including a gate and a gate dielectric layer, in which the gate dielectric layer covers sidewalls and a bottom of the gate; a channel layer located on a side of the gate dielectric layer away from the gate, in which the channel layer includes a metal oxide semiconductor layer, in which the active area includes a first active layer and a second active layer located at two sides of the gate structure, and the first active layer and the second active layer are in contact with the channel layer.

Abstract: A refresh address generation circuit includes: a refresh control circuit configured to sequentially receive first refresh commands and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset value or output a second clock signal when the number of the first refresh operations is equal to the preset value n, where n is a positive integer greater than or equal to 1; an address generator coupled to refresh control circuit, pre-storing a first address, receiving the first clock signal or the second clock signal, outputting a first to-be-refreshed address in response to the first clock signal during each first refresh operation, the first to-be-refreshed address includes the first address, and changing the first address in response to the second clock signal.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a switching transistor and a storage transistor. The switching transistor includes a first gate electrode, a first channel layer coating a portion of the first gate electrode, and a first source-drain electrode and a second source-drain electrode both covering a surface of the first channel layer. The storage transistor includes a second gate electrode, a second channel layer coating a portion of the second gate electrode, and a third source-drain electrode and a fourth source-drain electrode both covering a surface of the second channel layer. A portion of the second gate electrode extending out of the second channel layer in a first direction is electrically connected to the second source-drain electrode. The storage transistor is configured to store charge.

Abstract: A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.

Abstract: A refresh control circuit includes: a processing circuit, configured to receive a refresh command signal, and perform pulse combination processing on the refresh command signal to obtain a refresh combined signal, the refresh command signal having a plurality of pulses in a first time period and keeping a level state unchanged in a second time period, and the first time period and the second time period existing alternately; a logic circuit, configured to receive the refresh command signal and the refresh combined signal, and perform logical operation processing on the refresh command signal and the refresh combined signal to obtain a target control signal; and a power supply circuit, configured to receive the target control signal, and determine whether to perform a power supply operation according to the level state of the target control signal.

Abstract: A device, including a body including a first post and a second post positioned on opposite sides of a recessed area is disclosed. An assembly including the device is disclosed. A method of using the device is also disclosed.

Abstract: A circuit for calibration control includes an off-chip calibration circuit and a mode switching circuit, and the off-chip calibration circuit includes a preprocessing circuit and a mapping circuit. The preprocessing circuit is configured to receive a current set of environmental parameters, decode the current set of environmental parameters and output parameter decoding signals. The mapping circuit is configured to receive the parameter decoding signals and output a first calibration code according to the parameter decoding signals. The mode switching circuit is configured to receive a calibration mode signal and the first calibration code, and determine the first calibration code as a ZQ calibration code in a case where the calibration mode signal indicates an off-chip calibration mode.

Abstract: A computing apparatus and method for proof of work, and a chip are provided. The computing apparatus includes: N selectors, respectively configured to obtain N groups of first input quantities; and N first compressors, respectively connected to the N selectors, and respectively configured to receive the N groups of first input quantities sent by the N selectors, and to receive a same second input quantity, wherein each first compressor is configured to sequentially perform compression processing on the second input quantity and each first input quantity in one group of first input quantities, and compression processing results of the N first compressors each is used to obtain a proof-of-work result.

Abstract: A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.

Abstract: A method and apparatus for testing a command are provided. The method includes that: when the test platform exists a target command to be sent to a memory, a duration of a deselect command is determined according to a minimum time interval between a target command and each of historical commands and the time when the each of the historical commands is sent and the present time; the target command is sent to the memory after the deselect command.

Abstract: The application provides a Word Line (WL) drive circuit and a Dynamic Random Access Memory (DRAM). The WL drive circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate of the first transistor is connected to a WL switch-off voltage, a drain is connected to the WL; a gate of the second transistor is connected to a first drive voltage of the WL, a drain is connected to the WL; and a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor.

Abstract: Methods and apparatuses to obtain increased performance and differentiation for an inductive position sensor through improvements to the sense element and target design are disclosed. In a particular embodiment, a sense element includes a transmit coil, a first receive coil that includes a first plurality of arrayed loops, wherein two or more of the first plurality of arrayed loops are at least one of phase blended and amplitude arrayed, and a second receive coil that includes a second plurality of arrayed loops, wherein two or more of the second plurality of arrayed loops are at least one of phase blended and amplitude arrayed, and wherein the first receive coil and the second receive coil are phase shifted. The sense element coils are arrayed in several geometries and layouts, and the coil and target geometry are manipulated to compensate for inherent errors in the fundamental design of an inductive position sensor.