Abstract: A method and device for Fail Bit (FB) repairing. The method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on first FBs in each target repair bank using a redundant circuit; second FBs are determined, and second repair processing is performed on the second FBs through a state judgment repair operation; for each target repair bank, unrepaired FBs in the target repair bank is determined, and candidate repair combinations and candidate repair costs of the unrepaired FBs are determined using an optimal combined detection manner; and a target repair cost is determined according to the candidate repair costs, and a target repair solution corresponding to the target repair cost is determined to perform repair processing on the unrepaired FBs according to the target repair solution.

Abstract: Systems, methods, and related technologies for generating a network system map based on network traffic and possibly additional data are described. Network traffic may be received and parsed to obtain metadata associated with the network traffic. A network system may be identified based on the metadata. A network system map may be generated for the network system based on one or more of the metadata or the additional data.

Abstract: A manufacturing method of a semiconductor structure includes: providing a target layer; forming a plurality of first mask patterns on a top surface of the target layer; forming a plurality of second mask patterns above the target layer, where each of the second mask patterns covers at least a part of a top surface of each of the first mask patterns and a part of the top surface of the target layer in an extension direction of the second mask pattern; performing a first etching on the target layer based on the second mask patterns; removing the second mask patterns; and performing a second etching on the target layer based on the first mask patterns.

Abstract: Provided are standby circuit dispatch method, apparatus, device and medium. The method includes: a first test item is executed and first test data is acquired, the first test data including position data of a failure bit acquired during execution of the first test item; a first redundant circuit dispatch result is determined according to the first test data; a second test item is executed and second test data is acquired; when the failure bit acquired during execution of the second test item includes a failure bit outside the repair range of the dispatched regional redundant circuits and dispatched global redundant circuits, and the dispatchable redundant circuits have been dispatched out, a maximum target bit umber is acquired according to the first test data and the second test data; and a target dispatch mode is selected and a second redundant circuit dispatch result is determined according to the target dispatch mode.

Abstract: A folded Marchand Balun includes a first, a second, a third port, and a first transmission line being folded into a first and second intermediate transmission lines, the first intermediate transmission line disposed on a first signal plane and electrically connected through metal vias to the second intermediate transmission line disposed on a second signal plane. The first transmission line has one end as the first port and an opposite end as an open circuit. The Balun includes a second transmission line disposed on the first signal plane and is adjacent to the first intermediate transmission line. The second transmission line has one end as the second port and an opposite end grounded. The Balun includes a third transmission line disposed on the second signal plane and adjacent to the second intermediate transmission line. The third transmission line has one end as the third port and an opposite end grounded.

Abstract: A gaming machine includes an input device and a processor coupled to the input device. The input device is configured to receive a game play event from a player. The processor is programmed to determine whether a jackpot trigger condition is satisfied based at least in part on the game play event. The jackpot trigger condition includes a target quantity of games played, a target set of game tokens, a target pattern of game symbols, and/or a target pattern of game play outcomes. The processor is further programmed to award a jackpot credit to one or more players when the jackpot trigger condition is satisfied.

Abstract: A simulation method implemented at least in part at a node of a blockchain network enables detection of suspected malicious behaviour. When a purchase of a token of interest by a user is detected, information about other queued transactions awaiting committal to the blockchain is retrieved, and a batch of probing transactions is constructed using the information about the queued transactions. The batch includes a probing transaction representing a sale of the token by the user. At the node, the state of the blockchain is overridden so that the user's wallet and other wallets appear to contain bytecode executable to aggregate multiple transactions into a single call, and the batch of transactions is thus executed in a single call. The results are evaluated to determine whether the sale of the token by the user was successful. If the evaluation is not successful, remedial action may be taken.

Abstract: The embodiments relate to a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a wafer, in the wafer there being provided with a scribe line, in the scribe line there being provided with a test pad, a first test structure, and a second test structure; the second test structure being positioned below the first test structure, and a transverse pitch between the second test structure and the first test structure being at least equal to a width of the test pad; forming a protective layer on the wafer, the protective layer at least covering the scribe line; and performing exposure and development on the protective layer, such that a thickness of the protective layer remained above the first test structure is greater than that of the protective layer remained above the second test structure.

Abstract: A cooling system includes a nozzle guide vane endwall. The nozzle guide vane endwall includes a first wall and a second wall. The first wall includes a first opening that extends completely through the first wall into a primary flow path of a high-pressure turbine. The second wall includes a second opening that extends completely through the second wall into an inner passageway of the nozzle guide vane endwall. The inner passageway is configured to direct a cooling fluid to the first opening and/or the second opening. The first and second opening are configured to receive a plug or a probe.

Abstract: An autonomous mobile device (AMD) operating in a first mode moves within a physical space to perform various tasks such as displaying information on a screen, following a user, and so forth. The first mode may involve the AMD moving or maintaining a particular pose. While the AMD is in the first mode, a user may apply an external force to the AMD to reposition the AMD to a desired pose. Application of this external force on the AMD is detected and results in the AMD transitioning to a second mode in which the AMD may be repositioned. While in the second mode, the user may reposition the AMD. The second mode may constrain the magnitude of the resulting movement, preventing the user from moving the AMD too quickly which could damage components within the AMD. Once the external force ceases, the AMD may transition back to the first mode.

Abstract: An apparatus, system, and method for measuring a temperature gradient in a layered environment includes a container having a sidewall. An acoustic transducer is positioned on or proximate to an exterior surface of the sidewall of the container. A signal is transmitted from the acoustic transducer into the sidewall of the container. A reflected signal is received by the acoustic transducer, or another acoustic transducer positioned on or proximate to the exterior surface of the sidewall. A computerized device has a processor and a computer-readable memory. The processor is configured to measure a temperature gradient of the reflected signal using an angle of incidence and refraction of the reflected signal. The temperature gradient indicates a temperature of a material within the container.

Abstract: A semiconductor structure includes a substrate and a conductive structure located above the substrate. The conductive structure includes a plurality of first conductive structures and second conductive structures that are spaced apart from each other and extend in a first direction. Lengths of the first conductive structures and lengths of the second conductive structures vary in steps. The lengths of the plurality of first conductive structures and the lengths of the plurality of second conductive structures vary in steps. The first conductive structures and the second conductive structures form Word Lines (WLs).

Abstract: A system comprising at least one hardware processor; and a non-transitory computer-readable storage medium having stored thereon program instructions, the program instructions executable by the at least one hardware processor to: receive computer source code for deploying in a cloud environment associated with a cloud computing platform, configure a first cloud environment on the cloud computing platform, wherein the configuring comprises implementing an initial access permissions scheme with respect to resources in the first cloud environment, configure a second cloud environment on the cloud computing platform, wherein the cloud-based environment comprises a cloud storage instance, store the received computer source code in the cloud storage instance, and implement an import infrastructure extension in the second cloud environment, to perform imports from the cloud storage instance directly into the first cloud computation environment.

Abstract: An apparatus is provided that includes a memory system that includes a memory controller coupled to a storage device capable of streaming data at a first data rate. The memory controller is configured to read a first amount of input data from the storage device at an input data rate equals the first data rate, and provide the first amount of input data at the input data rate to a hardware circuit. The hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate. The hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the storage device, a memory buffer, and the hardware circuit.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Abstract: Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

Abstract: An integrated artificial pancreas with multiple infusion modes, includes: drug infusion unit; program unit comprising input end and output end, and the input end comprises a plurality of electrically connective regions for receiving signals of analyte data in the body fluid, after the output end is electrically connected to the power unit, the program unit controls whether the drug infusion unit delivers drugs; and an infusion cannula provided with at least two detecting electrodes, the infusion cannula is the drug infusion channel, the electrodes are disposed on the cannula wall. It takes only one insertion to perform both analyte detection and drug infusion.

Abstract: A needle mechanism module for drug infusion device, includes: an infusion needle, provided with a front end and a rear end; a needle holder; provided with at least an auxiliary engaging part, the infusion needle being arranged on the needle holder, when the needle holder is at the working position, the rear end is inserted into the skin, and the front end is connected to the drug storage unit of the infusion device; an auxiliary engaging portion, arranged within the infusion device, engaged with the auxiliary engaging part to limit the needle holder at the working position; and a stopper, arranged on the housing of the infusion device, when the needle mechanism module is at intermediate position, the stopper limits the position of the needle holder, the front end is connected with the drug storage unit of the infusion device, to balance the internal and external pressures.

Abstract: A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.