Abstract: An electrostatic protection circuit for a chip including a power supply pad and a ground pad, the electrostatic protection circuit includes: a monitoring assembly, configured to generate a trigger signal when an electrostatic pulse is present on the power supply pad; a discharge transistor connected between the power pad and the ground pad and configured to be turned on under control of the trigger signal to discharge electrostatic charges to the ground pad; and a control circuit connected to the monitoring assembly and configured to control a duration of the trigger signal generated by the monitoring assembly.

Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.

Abstract: A board adapter device includes: a first adapter structure provided with a gold finger matched with a board of a target memory module, a second adapter structure provided with a connector matched with the gold finger, and a signal transmission structure including a first and second transmission module. The first transmission module is for connecting a data signal line, a clock signal line, an address signal line, and a control signal line of the gold finger to corresponding connecting lines of the connector. The second transmission module is configured to, when receiving a power input signal, convert the power input signal into a power output signal matched with a power supply of the target memory module, and transmit the power output signal to a power signal line of the connector.

Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.

Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.

Abstract: A memory read-write circuit includes a sense amplifier and a control signal generation module. A power voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and a first power voltage controlled and supplied by the first control signal is greater than a second power voltage controlled and supplied by the second control signal. A control signal generation module is configured to control, in a normal read-write mode, a pulse duration for generating the first control signal to be a first duration, and control, in a refresh mode, the pulse duration for generating the first control signal to be a second duration, the second duration being less than the first duration.

Abstract: A semiconductor memory device, also referred to as a solid state drive, includes thermally conductive components such as a conductive coating to draw heat away from the semiconductive package. The coating may also be electrically conductive to provide shielding from and absorption of electromagnetic interference. In examples, a semiconductor device including a substrate may be affixed to an edge connector printed circuit board with solder balls to form a solid state drive. In further examples, the substrate may be omitted, and semiconductor memory dies, a controller die and other electronic components may be directly surface mounted to an edge connector printed circuit board to form a solid state drive.

Abstract: The present application relates to a buried gate and a manufacturing method thereof. The method for manufacturing a buried gate includes: providing a substrate; forming a word line trench in the substrate; treating a surface of the word line trench to form concave structures on the surface of the word line trench; and, forming a conductive layer in the word line trench, convex structures matched with the concave structures being provided on a surface of the conductive layer.

Abstract: A method for manufacturing a semiconductor structure comprises: forming a stacked structure on a base having an array area and a peripheral area; forming a first mask layer on the stacked structure, in which the first mask layer corresponding to the array area has a first pattern; ion doping the first mask layer on the array area to obtain a doped first mask layer; and etching the stacked structure through the doped first mask layer to transfer the first pattern to the stacked structure.

Abstract: A mirror array includes a lid, a base, and a movable mirror between the lid and the base. The movable mirror includes a stationary frame including a cavity, a movable frame in the cavity, and a central stage in the cavity. The mirror array also includes a first protrusion on the base wafer. The first protrusion overlaps with the central stage in a first direction.

Abstract: The present disclosure provides a mask pattern for a semiconductor photolithography process and a semiconductor photolithography process. The mask pattern comprises: a pattern, the pattern comprising a light-transmitting area and a light-shielding area which are alternately arranged, the pattern having a boundary formed by an end portion of the light-transmitting area and an end portion of the light-shielding area, and an edge light-transmitting area being formed at the boundary. By the mask pattern of the present disclosure, a pattern with smooth edges can be formed on a wafer, and the edge roughness of the pattern is low, which meets the design requirements, thereby improving product quality and yield.

Abstract: Aspects of a storage device including at least one die and a controller are provided that allow superblock formation using surplus block pairs when bad blocks occur. After the controller forms a superblock including a first block in a first plane of the die and a second block in a second plane of the die, the controller identifies the first block as a bad block and switches the second block into a surplus state (or vice-versa). The controller then forms a new superblock from blocks in a spare pool. When the number of blocks is equal to a superblock threshold, the controller attempts to pair the surplus block with another surplus block from the opposite plane according to a die sequence. If the attempt to pair is successful, the controller adds the pair to the spare pool; otherwise, the surplus block is not added to the spare pool.

Abstract: A feature game presented on a gaming machine after a base game includes symbols having corresponding values which may be incremented based at least in part on a random determination during an instance of the feature game. Such symbols and their associated values may persist through one or more subsequent instances of the feature game. In some embodiments values of individual symbols may be incremented multiple times.

Abstract: Devices and techniques are generally described for a speech processing routing architecture. First input data representing an input request may be received. First data may be sent to a first skill representing a first request for the first skill to evaluate an ability of the first skill to process the first input data. Second data may be sent to a second skill representing a second request for the second skill to evaluate an ability of the second skill to process the first input data. Third data may be received from the first skill indicating a first action performed by the first skill in response to receipt of the first input data. Fourth data may be received from the second skill indicating a second action performed by the second skill. The first skill may be selected for processing the first input data.

Abstract: A battery testing apparatus includes a battery cycler configured to position a battery cell in a cell pocket defined by a baseplate. The apparatus additionally includes a thermal control device configured to regulate thermal energy in the cell pocket, a baseplate thermistor for detecting baseplate temperature, and thermal control device thermistor for detecting thermal control device temperature. The apparatus also includes a printed circuit board (PCB) in electric communication with the thermal control device thermistor. An electronic microcontroller, in electric communication with the baseplate thermistor and the PCB, is configured to regulate operation of the thermal control device based on data from the baseplate thermistor and the thermal control device thermistor.

Abstract: Systems and methods for managing network connectivity of speech processing-enabled devices are provided. The speech-enabled device may periodically monitor a variety of metrics related to the network connectivity status of the device, and save those metrics in a local events log. The speech-enabled device may then periodically send those metrics to a remote speech processing management system. Users may then use voice commands to request the status of the speech-enabled device, and the speech-enabled device will send that request to the speech processing management system. The speech processing management system can then retrieve the historical metrics for that device and determine one or more inferences regarding the condition of the device. These inferences are used to diagnose potential network connectivity problems being experienced by the speech-enabled device, and to generate recommendations for remediating those problems.

Abstract: A method of detecting anomalous behaviour in data traffic on a data communication network having a first host and a second host being connected to the data communication network in which the data traffic on the data communication network forms a link between the first host and the second host.

Abstract: Particulate composite materials and devices comprising the same are provided.

Abstract: A high-voltage (HV) power supply outputs an output voltage based on a control signal produced by a dual analog/digital feedback loop. The control signal is determined at least in part by an error amplifier that receives a measurement signal, proportionally attenuated from the output voltage, and a digital-to-analog converter (DAC) output signal. An analog-to-digital converter (ADC) also receives the measurement signal and transmits it in digitized form to a digital processor. The digital processor calculates a digital DAC data signal based on the measurement signal, and on a digital set-point input signal corresponding to a set-point voltage value of the output voltage desired to be outputted from the high-voltage source. A DAC receives the DAC data signal and converts it to the DAC output signal transmitted to the error amplifier.