Patents Assigned to TECHNOLOGIES INC.
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Patent number: 11217039Abstract: An illustrative example method of monitoring value added activity includes positioning a detector near a selected portion of a machine using a clip for situating the detector in a position where the detector can detect at least one electrical characteristic associated with operation of a machine; communicating an indication of the detected electrical characteristic between the detector and a user interface; and displaying a visual representation of value added activity information based the indication. The value added activity corresponds to human operator performance that is distinct from machine performance during a manufacturing or assembly process.Type: GrantFiled: September 15, 2020Date of Patent: January 4, 2022Assignee: FREEPOINT TECHNOLOGIES INC.Inventors: Paul Hogendoorn, Sophear Net, William Favaro, Michael J. Foster, Daniel Kaptur, Gregory Jacobs
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Patent number: 11216445Abstract: A first state identifier is determined according to the state of a first file at a first time point, and a second state identifier is determined according to the state of a second file at a second time point. The first and second state identifiers are compared and an alignment indication is displayed to a user of a client device thereby making the user aware of the alignment state between the files. The files may be associated with different client devices or different users thereby showing group alignment. The files may also be associated with a single user or client device thereby showing local alignment. The state identifiers may include digest hashes of content of the first and second files, metadata, or state information regarding the files. The files may be encrypted and access check keys utilized to determine whether a client device is authorized to receive an encrypted file.Type: GrantFiled: June 4, 2019Date of Patent: January 4, 2022Assignee: ULTRALIGHT TECHNOLOGIES INC.Inventor: Charles C. Gammans
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Patent number: 11213829Abstract: A comminution system for heterogeneous materials includes pumps, a source of liquid in fluid communication with the pumps, a source of heterogeneous material, a mixer to combine the heterogeneous material and the liquid, and nozzles in fluid communication with the pumps, respectively. The pumps are in straight-line alignment with the nozzles. The nozzles receiving the heterogeneous material combined with the liquid direct the combined slurry to an impact zone where the fractions of the heterogeneous material are disassociated.Type: GrantFiled: October 10, 2019Date of Patent: January 4, 2022Assignee: DISA TECHNOLOGIES, INC.Inventors: Eric Coates, John Lee
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Patent number: 11216696Abstract: Exemplary methods and apparatus are provided for configuring a data storage controller to select training data samples from a non-volatile memory (NVM) array for forwarding to an external machine learning processor. The machine learning processor trains a deep neural network model by, e.g., performing various forward and backward passes through a neural network. Within illustrative examples, the data storage controller is equipped with a data sample selection unit that intelligently selects training data stored in the NVM array to forward to the external machine learning processor to reduce an amount of training data to be transferred to the machine learning processor. Among other features, this allows for the practical use of NVM arrays (such as NAND memory arrays) for storing large quantities of machine learning training data, rather than high-speed volatile memory (such as dynamic random access memory), which may be impractical and cost-prohibitive for low-power applications.Type: GrantFiled: February 6, 2020Date of Patent: January 4, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ariel Navon, Shay Benisty
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Patent number: 11216184Abstract: Methods and apparatus are disclosed for implementing principal component analysis (PCA) within a non-volatile memory (NVM) die of solid state drive (SSD) to reduce the dimensionality of machine learning data before the data is transferred to other components of the SSD, such as to a data storage controller equipped with a machine learning engine. The machine learning data may include, for example, training images for training an image recognition system in which the SSD is installed. In some examples, the on-chip PCA components of the NVM die are configured as under-the-array or next-to-the-array components. In other examples, one or more arrays of the NVM die are configured as multiplication cores for performing PCA matrix multiplication. In still other aspects, multiple NVM dies are arranged in parallel, each with on-chip PCA components to permit parallel concurrent on-chip processing of machine learning data.Type: GrantFiled: December 6, 2019Date of Patent: January 4, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Won Ho Choi, Yongjune Kim, Martin Lueker-Boden
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Patent number: 11218375Abstract: Embodiments of the present disclosure generally relate to a cloud computing network and a method of transferring information among processing nodes in a cloud computing network. In one embodiment, a cloud computing network is disclosed herein. The cloud computing network includes a plurality of motherboards arranged in racks. Each individual motherboard includes a central hub and a plurality of processing nodes equipped to the central hub. Each processing node is configured to access memory or storage space of another processing node in the same motherboard by intermediation of the hub. The access is called a communication between a pair of processing nodes. The communication includes a string of information transmitted between processing nodes. The string of information has a plurality of frames. Each frame includes a plurality of time slots, wherein each time slot is allotted a specific node pair.Type: GrantFiled: March 25, 2020Date of Patent: January 4, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Luiz M. Franca-Neto
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Patent number: 11217374Abstract: Magnet array structure and method for forming magnet array structure that includes a first linear magnet array including a first magnet arrangement, in which the first magnet arrangement is consecutively repeated and a second linear magnet array including a second magnet arrangement, in which the second magnet arrangement is consecutively repeated. The first magnet arrangement includes a plurality of first magnetic elements having non-uniformly dimensioned widths in a length direction of the first magnet arrangement and the second magnet arrangement includes a plurality of second magnetic elements having non-uniformly dimensioned widths in a length direction of the second magnet arrangement. The first linear magnet array is arranged parallel to the second linear magnet array so that the first magnet arrangement is linearly offset from the second magnet arrangement.Type: GrantFiled: August 6, 2020Date of Patent: January 4, 2022Assignee: HYPERLOOP TECHNOLOGIES, INC.Inventor: Casey Handmer
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Publication number: 20210408900Abstract: A charge pump circuit includes: a charge pump core circuit configured to generate an output voltage, an oscillator configured to provide a clock signal for the charge pump core circuit, and a feedback circuit configured to control the oscillator based on the output voltage, wherein the feedback circuit includes an inner loop.Type: ApplicationFiled: August 21, 2021Publication date: December 30, 2021Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Haining XU
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Publication number: 20210408228Abstract: A method for forming a semiconductor device includes: a substrate is provided; a barrier layer is formed on an upper surface of the substrate, and a proportion of crystal orientation <111> in crystal orientations of the barrier layer is at least a preset value; and a metal material layer is formed on an upper surface of the barrier layer, crystal orientations of the metal material layer including a crystal orientation <111>.Type: ApplicationFiled: August 26, 2021Publication date: December 30, 2021Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Xiguang LIU
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Publication number: 20210407558Abstract: A sense amplifier includes a first switch unit, a second switch unit, and an amplifier-latch module. A first port of the amplifier-latch module is electrically connected, via the first switch unit, to a bit line connected with a storage unit, and a second port of the amplifier-latch module is electrically connected to a reference voltage signal via the second switch unit. The amplifier-latch module is configured to amplify a signal in a sensing amplification phase. The first switch unit is configured to transmit a voltage on the bit line to the first port before the sensing amplification phase. The second switch unit is configured to transmit the reference voltage signal to the second port before the sensing amplification phase, and disconnect an electrical connection between the reference voltage signal and the second port in the sensing amplification phase.Type: ApplicationFiled: August 22, 2021Publication date: December 30, 2021Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: YING WANG, SUNSOO CHI
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Publication number: 20210408006Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes.Type: ApplicationFiled: September 8, 2021Publication date: December 30, 2021Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Yong LU
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Publication number: 20210404828Abstract: A methodology and system, devices and computing apparatus are presented for personalizing ride hailing services. A proprietary social media platform is integrated with a computing apparatus providing ride hailing services. The proprietary social media platform allows users and drivers to selectively share comments, posts and ratings that are used to personalize rides and increase the quality of taxi-like services while minimizing risks and helping drivers better monetize the taxi-like services.Type: ApplicationFiled: October 20, 2020Publication date: December 30, 2021Applicant: QUDOS TECHNOLOGIES INC.Inventor: NEIL ANTHONY ROLLON
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Publication number: 20210407554Abstract: A semiconductor device includes a storage chip and a temperature sensor for detecting the temperature of the storage chip, the temperature sensor and the storage chip being powered by different power supplies. The storage chip and the temperature sensor can use different power supplies. As such, the activations of both of them can be controlled separately, i.e., the activation of the temperature sensor is free from whether a storage chip is activated, so that the detection of the temperature of the storage chip is not affected by whether a storage chip is activated, thereby providing a reference for the activation and operation of the storage chip, and in turn avoiding the activation or operation of the storage chip under low temperatures and improving the stability of the storage chip.Type: ApplicationFiled: July 14, 2021Publication date: December 30, 2021Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Shuliang NING
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Publication number: 20210406162Abstract: The invention discloses a code testing method. The method includes the following steps of: acquiring a code set to be tested; loading the code set to a corresponding operating chip, and executing the code set by using the operating chip; judging whether a target code subset which is not successfully executed exists in the code set; and if yes, performing an audit testing operation on the code set. The code testing method provided by the invention is simple and feasible to apply, which improves a testing reliability and reduces a testing cost. The invention also discloses a code testing apparatus and device, and a storage medium, which have corresponding technical effects.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Applicant: HANGZHOU VANGO TECHNOLOGIES,INC.Inventors: Jie HE, Nick Nianxiong Tan, Xuening JIANG
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Publication number: 20210407576Abstract: A memory bank includes at least one storage module, each storage module including a read-write control circuit, a column decoding circuit and a plurality of storage arrays, the plurality of storage arrays being divided into a first unit and a second unit; a first decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the first unit; a second decoding selective signal line, electrically connected to the column decoding circuit and the storage arrays in the second unit; a first data signal line; and a second data signal line.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Weibing SHANG, Hongwen LI
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Publication number: 20210407670Abstract: A computer-implemented system may include a treatment device configured to be manipulated by a user while the user is performing a treatment plan, a patient interface comprising an output device configured to present telemedicine information associated with a telemedicine session, and a first computing device configured to: receive treatment data pertaining to the user while the user uses the treatment device to perform the treatment plan; identify at least one aspect of the at least one measurement pertaining to the user associated with a first treatment device mode of the treatment device; determine whether the at least one aspect of the measurement correlates with a secondary condition of the user; and, in response to a determination that the at least one aspect of the at least one measurement is correlated with the at least one secondary condition of the user, generate secondary condition information indicating at least the secondary condition.Type: ApplicationFiled: September 13, 2021Publication date: December 30, 2021Applicant: ROM TECHNOLOGIES, INC.Inventors: Steven Mason, Daniel Posnack, Peter Arn, Wendy Para, S. Adam Hacking, Micheal Mueller, Joseph Guaneri, Jonathan Greene
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Patent number: 11211119Abstract: Data can be written to SLC memory. Then, the data can be decoded and then both foggy and finely written to MLC. After the decoding, the data can be stored in DRAM located in a front end or in a SRAM located in a flash manager prior to being written to MLC. After storing in either the DRAM or SRAM, the data is then decoded and written to MLC.Type: GrantFiled: June 11, 2020Date of Patent: December 28, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Sergey Anatolievich Gorobets, Alan D. Bennett, Thomas Hugh Shippey, Ryan R. Jones
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Patent number: 11211172Abstract: Systems and methods that facilitate forming and maintaining FRCs with superior stability as well as particle, energy and flux confinement and, more particularly, systems and methods that facilitate forming and maintaining FRCs with elevated system energies and improved sustainment utilizing multi-scaled capture type vacuum pumping.Type: GrantFiled: April 30, 2019Date of Patent: December 28, 2021Assignee: TAE TECHNOLOGIES, INC.Inventor: Alan Van Drie
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Patent number: 11211083Abstract: Embodiments of the present disclosure generally relate to a write head for a magnetic recording device. The write head includes a spin torque oscillator (STO) that has a seed layer formed on a write pole, a spin polarization layer (SPL) formed on the seed layer, a first spacer layer formed on the SPL, a field generation layer (FGL) formed on the first spacer layer, a second spacer layer formed on the FGL, and a notch formed on the second spacer layer. The FGL and the notch are antiferromagnetically coupled through the second spacer layer and thus increases the FGL angle and improves the write capabilities of the write head.Type: GrantFiled: June 24, 2020Date of Patent: December 28, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yuankai Zheng, Zheng Gao, Christian Kaiser, Zhitao Diao, Susumu Okamura, James Mac Freitag, Alexander Goncharov
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Patent number: D939367Type: GrantFiled: July 15, 2019Date of Patent: December 28, 2021Assignee: FARO TECHNOLOGIES, INC.Inventors: Axel Ruhland, Jonas Bader, Benjamin Müller, Matthias Gramenz