Patents Assigned to Technology, Inc.
  • Patent number: 11158952
    Abstract: Technologies directed to cylindrical antenna structures. One metallic cylindrical antenna structure includes a first surface, a second surface, and a side wall with a first height. The cylindrical antenna structure can have a low profile with the first height being less than 20 millimeters (mm). The side wall includes first and second slots, the first being centered at a first point on the side wall at a second height and oriented longitudinally along an azimuthal direction of the cylindrical antenna structure and the second being centered at a second point on the side wall at the second height and oriented longitudinally along the azimuthal direction. A feed structure is located on the center axis and is physically separated from the first and second surfaces. The cylindrical antenna structure radiates electromagnetic energy in an omnidirectional radiation pattern, responsive to a radio frequency (RF) signal being applied to the feed structure.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 26, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Mohammed Ziaul Azad, Chen Chen, Amit Gaikwad, In Chul Hyun
  • Patent number: 11157400
    Abstract: A garbage collection operation can be performed on one or more data blocks of a memory sub-system, where data is stored at the one or more data blocks using a first write mode. In response to determining that the garbage collection operation satisfies a performance condition, a determination is made as to whether a data block of a cache area of the memory sub-system satisfies an endurance condition, where data is stored at the data block of the cache area using a second write mode. A write mode for the data block of the cache area is changed from the second write mode to the first write mode responsive to determining that the data block satisfies the endurance condition. The data block of the cache area is then used in the garbage collection operation.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Sampath K. Ratnam, Ashutosh Malshe
  • Patent number: 11157417
    Abstract: The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher S. Hale, Sampath K. Ratnam, Kishore K. Muchherla
  • Patent number: 11158067
    Abstract: The present embodiments relate to improvements to audio/video (A/V) recording and communication devices, including improved approaches to using a neighborhood alert mode for triggering multi-device recording, to a multi-camera motion tracking process, and to a multi-camera event stitching process to create a series of “storyboard” images for activity taking place across the fields of view of multiple cameras, within a predetermined time period, for the A/V recording and communication devices.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 26, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: John Modestine, Joshua Roth
  • Patent number: 11159335
    Abstract: Systems and methods provide for managing a power consumption policy for a powered device. A network controller may be configured to receive power consumption information for a powered device (PD) connected to power sourcing equipment (e.g., a PSE device), calculate a predicted threshold for the PD based on the power consumption information for the PD, and transmit the predicted threshold for the PD to the PSE device. Power sourcing equipment is configured to calculate power consumption information for the PD, transmit the power consumption information for the PD to the network controller, receive a predicted threshold for the PD, and implement a power consumption policy for the PD based on the predicted threshold.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: October 26, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Amitesh Shukla, Jigar Amin, Manish Jhanji, Rakesh Mishra
  • Patent number: 11154382
    Abstract: In one aspect, an orthodontic appliance can include a shell having a plurality of cavities shaped to receive a patient's teeth. The shell can include an exterior layer and an interior layer having a stiffness less than a stiffness of the exterior layer. A discontinuity can be formed in the exterior layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: October 26, 2021
    Assignee: Align Technology, Inc.
    Inventors: Avi Kopelman, Jeeyoung Choi
  • Patent number: 11159970
    Abstract: In one embodiment, an apparatus comprises a compressive sensing schedule generator configured to generate a plurality of compressive sensing schedules, wherein each of the plurality of compressive sensing schedules is for each of a plurality of frequency bands of a network, wherein the network comprises a plurality of access points and a plurality of clients, and a sensing matrix combiner configured to combine the plurality of compressive sensing schedules into a resulting schedule that comprises a spatial distribution and a scheduled time slot for each of the plurality of access points.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 26, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Khashayar Mirfakhraei, Xu Zhang, Ardalan Alizadeh, Amir Hosein Kamalizad
  • Patent number: 11160162
    Abstract: Disclosed herein are multi-layer metal circuits, such as printed circuit boards (PCBs), with single-sided, partially-shielded, or fully-shielded via-less common-mode filters. The multi-layer metal circuits comprise at least one shield layer, at least one signal trace, and at least one reference layer (e.g., ground). The reference layer comprises a pattern of the via-less common-mode filter. The pattern may comprise, for example, a single piece-wise linear segment, or two or more disjoint and non-intersecting segments (which may be strictly linear or piece-wise linear). The reference layer is electrically isolated from the shield layer, and thus the via-less common-mode filters do not require vias. In addition to being used in PCBs, the disclosed multi-layer metal circuits may also be used in other applications, such as integrated circuits (e.g., implemented in semiconductor chips).
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Xinzhi Xing, Antonio Ciccomancini Scogna, Jack Nguyen
  • Patent number: 11157186
    Abstract: Systems and methods for distributed storage systems using dynamic spreading policies are described. Distributed storage elements may be accessed using various storage paths through hierarchically organized storage system components to store data blocks corresponding to data elements. A higher priority hierarchical spreading policy is selected for determining the storage elements to receive the data blocks. If the first hierarchical spreading policy is determined not to have been met, a lower priority hierarchical spreading policy is selected and the data blocks are stored according to the lower priority hierarchical spreading policy. Data block stored at the lower priority hierarchical spreading policy may automatically be migrated to the higher priority hierarchical spreading policy.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: October 26, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sam De Roeck, Arne De Coninck, Stijn Devriendt, Lien Boelaert, Annelies Cuvelier, Frederik De Schrijver
  • Patent number: 11158577
    Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Biow Hiem Ong, David A. Daycock, Chieh Hsien Quek, Chii Wean Calvin Chen, Christian George Emor, Wing Yu Lo
  • Patent number: 11159528
    Abstract: Systems and methods are described for facilitating authentication of hosted network services to other services. A target service, such as a database, may require specific authentication information, such as a username and password, to access the target service. While this information could be manually specified in the hosted network service, de-centralized storage of authentication information is generally discouraged by security best practices. This disclosure provides an authentication proxy system that reduces or eliminates a need for hosted network services to store authentication information for target services. Rather, the authentication proxy system can obtain authentication information for the hosted network service that is provided by a hosting system, and authenticate the hosted network service using that authentication information.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 26, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Adam Charles Siefker, Sean Oczkowski, David Richardson, Samvid H. Dwarakanath, Marc John Brooker, Orr Weinstein
  • Patent number: 11158387
    Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Deping He, Jingyuan Miao
  • Patent number: 11159960
    Abstract: Systems and methods herein can synchronize 802.11ax Uplink (UL) and Downlink (DL) Orthogonal Frequency-Division Multiple Access (OFDMA) schedules between adjacent APs that have overlapping BSSs, which may not be solved by BSS coloring. The method includes several stages. First, the APs detect RF interference from APs with overlapping BSSs. Then, the APs conduct time synchronization between these APs. The various APs can then elect a master scheduler. The master scheduler creates and implements a master schedule between these APs to coordinate use of the radio resource.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 26, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Robert E. Barton, Vishal Satyendra Desai, Indermeet Singh Gandhi, Jerome Henry
  • Patent number: 11155005
    Abstract: Techniques for 3-D printing a tooling shell for use in producing panels for a transport structure, such as an automobile, boat, aircraft, or other vehicle, or other mechanical structure, are disclosed. A 3-D printer may be used to produce a tooling shell containing Invar and/or some other material for use in molding the panels. A channel may be formed in a 3-D printed tooling shell for enabling resin infusion, vacuum generation or heat transfer. Alternatively, or in addition to, one or more hollow sections may be formed within the 3-D printed tooling shell for reducing a weight of the shell.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: October 26, 2021
    Assignee: DIVERGENT TECHNOLOGIES, INC.
    Inventors: Jon Paul Gunner, Narender Shankar Lakshman
  • Patent number: 11158608
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 26, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Kuang-Jen Shen, Chen-Pei Hsieh
  • Patent number: 11158393
    Abstract: Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 11156658
    Abstract: Techniques for memory I/O tests using integrated test data paths are provided. In an example, a method for operating input/output data paths of a memory apparatus can include receiving, during a first mode, non-test information at a data terminal of a first channel of the memory apparatus from a memory array of the first channel via a first data path, receiving during a first test mode, first test information at the data terminal of the first channel from a first additional data path coupling the first channel with a second channel of the memory apparatus, and wherein an interface die of the memory apparatus includes the first data path and the additional data path.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Chiaki Dono
  • Patent number: 11157740
    Abstract: Systems and methods for displaying digital objects in multiple configurations based on a placement location within an Augmented Reality (AR) display. The systems are enabled to receive image data, identify multiple horizontal surfaces within the image data, and place a digital object model within the image data. The digital object model is placed in the AR display in a first configuration when placed with an anchor of the digital object model on a first horizontal surface and in a second configuration when placed with the anchor on a second horizontal surface.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 26, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Mukul Agarwal, Kevin May, Xing Zhang, Karl Hillesland, Simon Fox, Jack Mousseau, Kai Chieh Liu
  • Patent number: 11159310
    Abstract: A digital security bubble encapsulation is disclosed. A public key and a device identifier of at least one recipient is requested from a first server. A message containing one or more components is encrypted using a symmetric key. The symmetric key is encrypted with a public key received in response to the request. The encrypted message, the encrypted symmetric key, and the device identifier are encapsulated in a digital security bubble encapsulation. The digital security bubble encapsulation is transmitted to a second server.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: October 26, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Christopher A. Howell, Robert Statica, Kara Lynn Coppa
  • Patent number: 11159481
    Abstract: A method is performed by a master network device among network devices of a cluster. The master network device receives cluster configuration information including a set of Internet Protocol (IP) addresses and a pool of port blocks associated with the IP addresses. Each port block includes multiple ports, and the pool of the port blocks is to be shared across the network devices for port address translation. The master network device divides the port blocks in the pool into multiple buckets. The master network device allocates to each network device in the cluster a corresponding one of the buckets, and reserves each bucket that is not allocated for allocation to a potential new network device. When a new network device joins the cluster, the master network device allocates to the new network device the port blocks from a corresponding one of the reserved buckets.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 26, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Andrew E. Ossipov, Kent Leung, Zhijun Liu