Abstract: A high-transconductance composite PNP transistor comprises a PNP transistor and three or more NPN transistors arranged in a three-terminal configuration which behaves as a PNP transistor, and yet exhibits high beta, alpha greater than one, and transconductance approaching infinity.

Abstract: Color dither patterns are read into a pixel bit map memory used to form a color display by means of concurrently addressing a pattern memory storing the dither patterns. Lower order address bits repeatedly access a preselected portion of the pattern memory to supply the dither pattern which is written as data into the pixel bit map memory.

Abstract: An air-assisted drop-on-demand ink jet head 10 has a single compartment ink chamber 14 and is designed for operation over a wide range of ink drop repetition rates, including extremely high repetition rates, such as twenty kilohertz. The components included in the ink jet head have natural resonance frequencies which are greater than the desired maximum drop generation frequency of the ink jet head. In addition, the natural frequency of each of the components of the ink jet head are sufficiently different from one another to prevent intercoupling. Ink is supplied to the ink chamber 14 via a supply inlet passageway 38 which has a cross-sectional area which is sized large enough to allow the supply of ink to the ink chamber. Yet, this area is small enough so that the natural frequencies of ink in the ink inlet do not significantly alter drop generating pressure pulses in the ink chamber 14.

Abstract: A method of testing an electronic circuit of the kind having an input port for receiving input vectors, an output port for providing output vectors, and a serial scan port for providing at least one serial scan vector reflecting the status of predetermined elements within the circuit, is performed by applying a sequence of test vectors to the input port as a plurality of sub-sequences each including at least one test vector. The serial scan vector is examined after each sub-sequence, and a determination is made as to whether a part of the serial scan vector indicates the presence of a defect in the circuit. In the event that part of the serial scan vector indicates the presence of a defect in the circuit, the corresponding part of a succeeding serial scan vector is prevented from indicating the presence of a defect.

Abstract: A power buffer circuit includes a power MOS device connected via a local feedback loop to a differential amplifier. The MOS device amplifies the power of an input signal to produce an output signal. The differential amplifier causes the output signal voltage to follow the input signal voltage by sensing a difference between the two voltages and generating in response a difference signal to the MOS device to change the output signal voltage level. The buffer circuit may be configured as a current source or a current sink that maintains unity voltage gain from the input to output signal. The power buffer circuit may be incorporated into a voltage regulator that maintains a remotely sensed output voltage substantially equal to a predetermined factor of a reference voltage via a second, outer feedback loop.

Abstract: Two metallic members are connected together over a defined area of respective surfaces of the members by providing at least one layer of metal on at least one of the surfaces. The or each layer of metal has at least one elementary component and is of essentially uniform composition over the defined area, and is of essentially uniform thickness over the defined area. The two surfaces are brought into confronting, contacting relationship, and heat is applied to cause the metal of the or each layer to melt, whereby the members are bonded together by an alloy having a melting point in the range from about 500 degrees C to about 900 degrees C.

Abstract: An electronic circuit for selectively generating two output pulses that differ in duration by a predetermined amount has a clock terminal for receiving clock transitions at precisely determined intervals and comprises first and second sequential logic devices, a combinational logic device and a network that couples the clock terminal of the circuit to the sequential logic devices and also couples the second sequential logic device to the combinational logic device. The first and second sequential logic devices each have a data input terminal, a clock input terminal and an output terminal, and each has a first state in which the output terminal is at one of two binary logic levels and a second state in which the output terminal is at the other of the two binary logic levels.

Abstract: An infinite dynamic range phase detector compares a test signal with a phase shifted reference signal which tracks the phase drift of the test signal. The incremental phase error between the test signal and the phase shifted reference signal is accumulated to provide an n*modulo(360) plus the increment between zero and 360 degrees output. A portion of the accumulated output is fed back as an offset which is applied to a reference signal to produce the phase shifted reference signal.

Abstract: A timebase generator includes a transistor switch performing a sweep gate function, alternately providing a current path for retrace and then disconnecting such current path to allow generation of a time base ramp. The bias current delivered to the switch is controlled to be at a high level for bringing about proper retrace, but at a low level at the beginning and ending of the time base sweep itself to prevent undesired transients and nonlinearity effects. The low current is maintained from the end of the retrace period until the start of the following retrace period. A baseline stabilizer loop comprises a transistor circuit for accurately predetermining the baseline reference wherein the emitter current of the transistor is controlled to a substantially constant value during operation for enhanced stability.

Abstract: Apparatus for comparing a stream of data characters with a predetermined string of test characters has an input device for receiving the stream of data characters and a main processor for generating the predetermined string of test characters. A hardware register receives the predetermined string of test characters from the main processor, and a comparator device compares the stream of data characters with the contents of the register device and generates a response in the event that a portion of the stream is identical to the string of test characters generated by the main processor. A second processor receives the response and sends a report to the main processor.

Abstract: A circuit for generating a succession of fast rising voltage pulses comprises an inductor connected between first and second circuit nodes, a step recovery diode connected between a reference potential level and the first circuit node, and a current switch having a first state in which it conducts current in one direction with respect to the second circuit node and a second state in which it conducts current in the opposite direction with respect to the second circuit node. An oscillator is connected to the current switch for alternately and repeatedly placing the current switch in its first state and its second state. Preferably, the oscillator comprises a SAW resonator having a high Q and a parallel LC tank circuit having a low Q, connected in a closed positive feedback loop.

Abstract: An ink jet head 10 has an ink chamber 14 which receives ink from an ink inlet passageway 38. Pressure pulses applied to the ink chamber cause the ejection of ink drops from an ink drop forming orifice 23 and toward printing medium. A purging outlet 41 communicates with the ink chamber through a purging passageway 40. During purging, ink flows in a vortical path through the ink chamber 14 from the ink inlet passageway 38 to the purging outlet passageway 40. This sweeps air bubbles and contaminants from the ink chamber walls and removes them from the ink chamber. Ink pressure within the ink chamber 14 may be elevated to increase the flow of ink during purging. Also, a negative pressure may be applied to the purging outlet during purging. Variable frequency pressure pulses may also be applied to the ink chamber to assist the purging process.

Abstract: A loop control system for digital processing apparatus. A dedicated storage register and associated counting register are provided for receiving a starting value representing a number of passes through a program loop. An iteration circuit is provided for receiving the value in the counting register, iterating it, and storing the new value in the same counting register with each successive pass through the loop. A detector is provided for comparing the output of the iteration circuit to a predetermined value and providing a completion signal when the new value and the ending value have a predetermined relative relationship. Control logic is provided for causing the value in the storage register to be transferred into the counting register upon the occurrence of an output signal from the detector circuit. A plurality of pairs of storage and counting registers may be provided for keeping track of the number of iterations of nested loops.

Abstract: A switchable color filter employs chiral liquid crystal circular polarizers to minimize the attenuation of light passing through a system in which it is incorporated. One preferred embodiment (12) of the switchable color filter includes a light modulator (32) positioned between the light polarizing assembly (20) and first and second chiral liquid crystal cells (36 and 38). The light polarizing assembly receives unpolarized light and transmits circularly polarized light of colors included within first and second narrow color bands. The first chiral cell reflects incident light within the first color band and in a first polarization state, and the second chiral cell reflects incident light within the second color band and in a second polarization state. The light modulator cooperates with a switching circuit (34) to selectively provide first and second polarization switching states.

Abstract: A system for assembling electronic work stations including multiple electronic units. The electronic units are provided as subassemblies, premounted into specially formed trays. Special slide engaging male and female mounting components have one of the components formed into the chassis and the other component formed into the tray. The subassemblies are simply slid into place and various locking means are automatically engaged as the subassemblies are forced into their "home" position. The assembly time is greatly reduced resulting in substantial savings.

Abstract: A single phase, buried channel charge coupled device has a high conductivity layer overlying the pinned regions thereof and extending to the channel stop regions, thereby facilitating the transfer of charge carriers between the channel stop regions and the pinned regions in order that the potential profile underlying said pinned regions may be more readily maintained. Extension of that high conductivity layer over the channel gate electrodes also facilitates the transmission of clocking voltages to the channel gate electrodes and allows the device to operate with decreased power losses.

Abstract: A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded including the condition of a lowest order stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.

Abstract: A charge coupled device (CCD) analog shift register in a two-channel serial-parallel-serial (SPS) structure operating in a fast-in/slow-out (FISO) mode for high speed signal acquisition and temporary storage of a plurality of samples. The two CCD arrays are clocked simultaneously, and the input analog signal is demultiplexed to the two arrays. Additional transfer electrodes are provided at the input of one of the arrays, and the other array is provided with a sampling clock which is 180.degree. out of phase with the sampling clock of the first array; two consecutive samples of the input signal are taken during each transfer clock cycle. All signal samples are clocked through the arrays simultaneously and appear at the output at the same time.

Abstract: A DC level shift circuit includes a differential amplifier with a level shift stage. The level shift stage has two portions for transmitting the input signals forming the differential signal through the level shift stage. A current source transmits the input signals through the level shift stage. Transistors with impedances substantially equal to the current source impedances are cross coupled to each input terminal. Each transistor senses a distortion signal produced by the current source impedance at one terminal and produces in response a correction signal. The correction signal is then transmitted to the other input terminal to be summed with the distortion signal there to pass the input signals through the level shift stage without distortion. The DC level shift stage is also responsive to another correction signal generated by a feedback control stage to control the common mode voltage of the amplifier.

Abstract: In accordance with the invention, a touch panel includes an electrically conductive film of a first resistivity which extends over a first area of a base plate. Regions of a resistivity higher than the first resistivity, such as discontinuities in the film, are positioned in this first area. These discontinuities are located so as to enhance the uniformity of an electric field which is established in a touch sensing portion of the film.