Abstract: A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places calibrated function codes which are then supplied to the pin electronics circuits.

Abstract: An electro-optical transducer module comprises a base member having a generally flat surface and a platform upstanding from the flat surface, an electro-optical transducer mounted on the platform, a fiber mount plate secured to the base member with one main face in confronting relationship with the generally flat surface of the base member, and an optical fiber secured to the fiber mount plate by way of its other main face. The optical fiber has an end face that is in optically-coupled relationship with the electro-optical transducer.

Abstract: A level shift circuit for shifting the common mode level of the output signal provided by a differential amplifier has first and second input terminals for receiving the output signal from the differential amplifier, which has a Thevenin source impedance R.sub.s, and also has first and second output terminals that are connected to a reference voltage level through a load impedance R.sub.o. The circuit comprises a differential transconductance amplifier having two output terminals that are connected respectively to the first and second output terminals of the circuit. The amplifier has the property that it responds to an input voltage E.sub.e between its input terminals by providing a current equal to E.sub.e g.sub.ml /(1+.tau.s) (where g.sub.ml is the transconductance of the amplifier, .tau. is the response time constant of the amplifier and s is the Laplace transform operator) at its output terminals.

Abstract: A replaceable RF connector with replaceable fuse has a receptacle mounted on a housing, the receptacle having a cavity and a throughole to the interior of the housing. An RF connector has a connector end for connecting cables and/or adaptors, a receptacle end having a fuse cavity in electrical connection with the connector end, and a flange integral between the connector end and the receptacle end. The receptacle end is configured to slide into the receptacle cavity such that a fuse electrically mounted in the fuse cavity has a lead extending through the receptacle throughole for connection to a circuit internal to the housing. A retainer ring slips over the RF connector such that the connector end protrudes, and is attached to the receptacle such that the RF connector is secured in the receptacle by the flange.

Abstract: A digital-to-analog converter comprises a current source for supplying a current of predetermined magnitude to a circuit node, and a switch connected to the circuit node, and defining a first current path leading to a reference potential terminal and a second current path leading to an output terminal. The switch has an input terminal, at which it receives a first digital signal of one binary digit for conversion to analog form, and also has a reference terminal, and has a first condition, when the voltage at the reference terminal is higher than that at the input terminal, in which the current supplied to the circuit node is delivered to the output terminal, and a second condition, when the voltage at the reference terminal is lower than that at the input terminal, in which the current is delivered to the reference potential terminal.

Abstract: A load-dependent current limiter for the power supply of a multi-module electronic system has a programming resistor in each module connected between the power supply voltage and a reference bus. The current through each programming resistor is proportional to the current requirements of the module. The voltage of the reference bus, which is proportional to the total current through all the programming resistors, is compared to the voltage developed across a sensing resistor by the total power supply current. When the sense voltage exceeds the reference voltage, indicative of tapping excess power, a signal is sent from the comparator to shutdown the power supply.

Abstract: In a graphics display system, a cursor is used to pan a viewport relative to a block of stored information only part of which is selectable to be viewed through the viewport. As long as a cursor remains within the viewport, it can be utilized in a conventional manner under the control of a mouse or the like to provide interaction with display information. When the cursor is moved outside the viewport of the display, the viewport is panned to include the cursor.

Abstract: An FET high frequency analog amplifier circuit employs a feed-forward technique to provide a first order correction of amplifier distortion. In one embodiment, the amplifier is configured as a differential set of cascode FET stages. A linearization stage is connected across the output cascode transistors to provide a cancellation signal to reduce amplifier nonlinearities. The linearizing circuit includes a pair of field effect transistors in source-coupled arrangement with their respective bases driven by the drains of the differential amplifier input transistors. The gates are further driven by biasing current sources. The drains of the linearizing transistors are cross connected to the drains of the cascode output transistors, thereby injecting a compensating error signal into each differential output node and cancelling circuit nonlinearities. The amplifier is well suited for fabrication in integrated circuit form, especially using gallium arsenide technology.

Abstract: A stereoscopic imaging system employs an image encoder that comprises a variable optical retarder which is positioned face-to-face with an image source and an image decoder that comprises only passive optical elements. In a first embodiment, the imaging system (50) uses a single variable optical retarder (22) to encode perspective view images by selectively developing zero and half-wave retardation. A passive viewing apparatus (52 and 54) employs retardation plates (56, 58, and 64) to decode the images. In a second embodiment, the imaging system (100) uses a pair of variable optical retarders (101 and 102) to encode perspective view images in left- and right-circularly polarized light. A passive viewing apparatus (106 and 108) employs quarter-wave plates (110 and 114) to decode the images. Each of the preferred embodiments is suitable for use with broadband image source phosphors and in processing perspective view images in full color.

Abstract: Apparatus for indicating proper compensation of an adjustable frequency compensation network comprises a signal source operable to apply a rectangular pulse train having a preselected peak magnitude to the frequency compensation network, and a peak detector circuit for comparing the output voltage of the frequency compensation network to at least one threshold value. The peak detector circuit is used to determine whether, at a time that follows a transition of a pulse of the pulse train by an interval that is less than one time constant of the frequency compensation network, the output voltage of the frequency compensation network bears a predetermined relationship to the threshold value.

Abstract: A cable strain relief clamp assembly to securely hold a bundle of flat cables while providing quick assembly/disassembly from the main unit chassis. Identical clamp halves are positioned and fastened at a specified location on the cable bundle. The clamp (with the attached cable) is then snapped onto a bracket to become a subassembly unit. The bracket mates with the main unit chassis utilizing a snap fit detail oriented perpendicular to typical cable axial forces, thus fixing the cables in place. Accommodating varied thicknesses and numbers of cables can be accomplished by varying the aperture of the clamp. The clamp may also provide an electrical ground path between cable and chassis. Other features of the present invention are that: (1) multiple cables and varied widths can be accomplished; (2) it can be detached from main unit chassis without use of fasteners; (3) it does not depend on termination of the cables in male/female relationship; and (4) a consistent part outline is provided for all applications.

Abstract: The present invention provides a parallel or "flash" analog-to-digital converter circuit (A) including a plurality of voltage comparators (20a-20g) arranged in first and second sets (F and E) adapted for receiving separate analog input signals. A push-pull configuration is employed in providing the analog input signal to the comparators of the two sets. The analog inputs (22a-22d) of the comparators (20a-20d) in the first set are provided in input signal V.sub.1 and the analog inputs (22e-22g) of the comparators (20e-20g) in the second set are provided an input signal V.sub.2 of equal magnitude but opposite polarity. Different reference voltages are provided to the reference inputs (24a-24g) of the comparators by a series-connected resistor network (H). Two encoders (I and J) and an adder (K) are used to detect the number of output signals from the comparators in a similar logic state and provide a digital binary output signal corresponding to the number of such outputs.

Abstract: A sample and hold network samples an input data signal at a periodic rate by differentiating the input data signal and multiplying it in an analog multiplier by a strobe signal, whose spectrum extends to at most twice the highest frequency in the data input signal. The output of the multiplier is combined in a differential amplifier with the input data signal to provide an output having a slope which is zero and also equal to the input data signal at times that are integral multiples of the period of the strobe signal.

Abstract: A shield structure for limiting transmission of electromagnetic radiation between two locations, one of which is inside the shield structure and the other of which is outside the shield structure, comprises first and second shell portions of electrically-conductive material. The first shell portion has a rim that defines an opening. A major part of the second shell portion corresponds substantially in shape to the shape of the opening, and its size is slightly smaller than that of the opening. One of the shell portions has tabs that are distributed about the opening and project towards the other shell portion. The tabs are electrically conductive, and provide electrically-conductive contact between the first and second shell portions.

Abstract: A method for automatically expanding and displaying a narrow pulse on an oscilloscope screen. The time sweep signal of the oscilloscope is first set to contain a predetermined number of input signal cycles. The speed of the time sweep is increased by an internal controller a number of settings to expand the signal cycle by a factor sufficient to place less than a single signal cycle within the sweep signal and an expanded singal pulse of greater than a specified duty factor outside the sweep signal. The dual trigger generators of the scope are set to trigger on opposite slopes of the pulse. If both trigger generators trigger, then the pulse is within the specified duty factor and the controller directs it to be displayed on the oscilloscope screen in its expanded form. The specified duty factor can be made exact by adjusting the duration of the sweep signal to match the duration of the duty factor once the period of the signal cycle is determined.

Abstract: A probe cable assembly for use in connecting a monitoring instrument to an electronic SUT, to analyze the interaction between the system and a multiple terminal electronic component which can be fitted in a receptacle of the system, comprises a flexible circuit cable having an instrument end and a probe end. The cable comprises at least a first group of conductors that terminate at the probe end of the cable in respective termination areas in a predetermined array. The termination areas are exposed to one side of the cable and form respective terminals for the conductors. The cable assembly also comprises a stiffening element attached to the cable at its probe end at the opposite side of the cable. The stiffening element is capable of fitting in the receptacle of the SUT. When the stiffening element is fitted in the receptacle of the SUT, the termination areas of the conductors make direct pressure contact with the terminals in the receptacle of the SUT.

Abstract: A method for providing test vectors adapted to test very large scale integrated circuit devices includes the steps of measuring testability employing a test counting procedure to provide a plurality of test count matrices. Sensitivity values are then enumerated by driving individual sensitivity values forwardly and rearwardly through the circuit, starting at the input terminals, until the test counts are accumulated. The enumerations define test vectors capable of testing the actual circuit. If the circuit includes reconvergent fanout loops, then these loops are enumerated first to provide partial solutions adopted during subsequent global enumeration.

Abstract: A voltage reference circuit (10) for a constant-current source transistor (16) of the bipolar type provides an output voltage in two components. The first voltage component varies in accordance with the negative temperature coefficient (C.sub.1) of the base (58)-emitter (78) junction of a bipolar transistor (60) to compensate for temperature-related changes in the base (18)-to-emitter (22) voltage of the constant current source transistor. The second voltage component is of fixed magnitude and develops collector current (I.sub.0) flow through the transistor and thereby actuates constant-current source operation. The result is a transistor constant-current source that provides a constant output current independent of temperature.

Abstract: A precision differential amplifier having unity-gain buffer amplifier input stages on each side of the amplifier includes a primary feedback path between the collector and base of the inside buffer amplifier transistor which operates when the differential amplifier is operated within its linear operating range. Under an overdrive signal condition, the primary feedback path is opened and a secondary feedback is activated to control the collector and base of the inside buffer amplifier transistor, thus preventing saturation of the inside buffer amplifier transistor and cutoff of the outside transistor. The primary and secondary feedback paths consist of only semiconductor junctions, minimizing heat and loading effects, reducing power supply voltage requirements, and facilitating rapid overdrive recovery.

Abstract: An active low-pass filter especially suitable for inclusion in an integrated circuit and capable of operating at frequencies up to at least f.sub.T /.beta. of transistors within the filter. A bootstrap circuit is coupled to the emitter follower to reduce the capacitive effect of the emitter follower on the passed signal and to guarantee precision pass band gain match among the filters. A plurality of active filters may be connected across the signal path to provide a selection of bandwidths. A filter is switched into and out of the signal path by selectively enabling and disabling its current source.