Abstract: Arbitrary sets of samples may be suppressed from display and analysis. The resulting record may then be saved in its abbreviated form or discarded. Such a record may also be retrieved and arbitrarily partially suppressed a second or third time, making a series of smaller and less complete acquisition histories. Each of these records may be saved with or without suppressed samples and may be later redisplayed reliably showing those samples originally saved.

Abstract: Bussing high frequency crosspoint switches is achieved by extending an output transmission line bus through an integrated circuit (IC) upon which the crosspoint switch is laid. The internal portion of the output transmission line bus is coupled to an output pad on the IC via a bond wire. This eliminates stubs from the output of the IC to the output transmission line as well as compensating for parasitic capacitance associated with the output pad.

Abstract: A method of mounting a banana-type electrical receptacle on the substrate includes the steps of placing the electrical receptacle over an aperture formed in the substrate with support ribs formed on the outer surface of the receptacle supporting the receptacle over the aperture. A deformable electrical lead extends from a centrally disposed conductive member making an electrical connection with an electrical contact on the substrate. The electrical lead is affixed to the electrical contact on the substrate and the receptacle is inserted into the aperture crushing or shearing the support ribs and the deforming the electrical lead. Alignment ribs formed on the outer surface of the receptacle have shoulders that contact the substrate for positioning the receptacle in the substrate. The mounting method is compatible with automated soldering processes, such as wave flow soldering.

Abstract: A bandpass sampling system (10) of this invention employs a conventional mixer (14) driven by a frequency-tunable LO (16) to upconvert a signal frequency band to an IF frequency band that is above the signal frequency band. The IF frequency band is passed through an IF bandpass filter (18) to provide to subsequent digitization stages (20, 24) an IF bandpass range of signal frequency components. In this architecture, the IF bandpass filter acts as an anti-alias filter for the digitization stages. The LO frequency is selected to place the upconverted signal frequency band within the pass band of the IF bandpass filter. The resultant IF bandpass signal is sampled and digitized at a rate that is commensurate with the IF bandwidth, but typically much lower than the IF bandpass center frequency. Signal sampling is carried out by a sample-and-hold or a track-and-hold circuit (20), the output of which is applied to an ADC (24) that is clocked (22) at the same rate as the sampling circuit.

Abstract: A method for calibrating an instrument includes maintaining typical response values at respective frequency locations. The response of the instrument being calibrated is measured at a subset of frequency locations in the typical response. Response values for frequency locations not in the subset are estimated from the typical and measured response values. The instrument is calibrated based on the actual and estimated response values. Apparatus for calibrating an instrument includes a signal generator, coupled to the instrument, which generates a signal having known characteristics. A controller, coupled to the instrument, generates a calibration signal. Controller memory stores typical response values at respective frequency locations, and measures response values at a subset of the frequency locations. Response values for frequency locations not in the subset are estimated from the typical and measured response values. The instrument is calibrated in response to the measured and estimated response values.

Abstract: An improved sub-range ADC uses a sigma delta converter which eliminates both the sample and hold and digital-to-analog converter circuits of prior sub-ranging ADCs. An input analog signal is applied to a sigma delta modulator that provides a one-bit output. The one-bit output is input to a first analog filter and a digital correction circuit. The output from the first analog filter and the input analog signal, suitably delayed and optionally filtered, are input to a difference amplifier that provides the input to an ADC. The output of the ADC also is input to the digital correction circuit. The digital correction circuit includes a digital decimation filter for the one-bit sigma delta modulator output to produce a multi-bit digital output that is added to, the output from the ADC. The resulting digital signal may be additionally digitally filtered to produce a converted digital signal that corresponds to the input analog signal.

Abstract: An electrical signal interconnect assembly has first and second high speed coaxial interconnects with each interconnect having a male and female side. One of the male and female side of the first interconnect is floatably mounted on the assembly with the other side mounted on an electrical instrument. The second coaxial interconnect is mounted on a mechanical alignment facility having coarse and fine mechanical alignment portions with the coarse mechanical alignment portion including a closely mating pocket and body. One of the male and female side of the interconnect is mounted on the pocket with the other side mounted on the body. One of the pocket and body is mounted on the interconnect assembly and the other of the pocket and body is mounted on the electrical instrument. A coaxial cable electrically connects the two coaxial interconnects together in the interconnect assembly.

Abstract: A service provider node has an active network daemon running on it. Users control an adaptive pipeline via the active network capability of the service provider node by sending coded instructions to the service provider node. An adaptive pipeline is constructed within the service provider node according to control parameters contained in the coded instructions sent to it by a user. The adaptive pipeline includes a decode and an encode stage with zero or more intermediate filtering stages. The number and type of intermediate stages is determined by the values of the specified flow parameters.

Abstract: A high precision sub-pixel spatial alignment of digital images, one from a reference video signal and another from a corresponding test video signal, uses an iterative process and incorporates spatial resampling along with basic correlation and estimation of fractional pixel shift. The corresponding images from the reference and test video signals are captured and a test block is overlaid on them at the same locations to include texture from the images. FFTs are performed within the test block in each image, and the FFTs are cross-correlated to develop a peak value representing a shift position between the images. A curve is fitted to the peak and neighboring values to find the nearest integer pixel shift position. The test block is shifted in the test image by the integer pixel shift position, and the FFT in the test image is repeated and correlated with the FFT from the reference image.

Abstract: A PALC panel which includes a layer of insulating material over the plasma electrodes and in which the cover sheet is spaced from the layer of insulating material at a distance of less than about 50 &mgr;m.

Abstract: A low temperature co-fired ceramic substrate structure has first and second conductive patterns respectively disposed on first and second dielectric layers with the conductive patterns being separated by the first dielectric layer. The first conductive pattern has a first conductive element functioning as a first plate of a capacitor and a second conductive element functioning as a voltage potential lead for an integrated circuit device. The second conductive pattern is positioned below the first conductive pattern and functions as the second plate of the capacitor and as a thermally conductive heat transfer layer for the integrated circuit device. At least a first thermally conductive via is formed between the top and bottom surfaces of the second dielectric layer and below the second conductive element with the via thermally coupled to the second conductive pattern. The thermal via or vias may be thermally coupled to a heat sink disposed adjacent to the bottom surface of the second dielectric layer.

Abstract: A quality cause measurement display is formed by generating an ideal digitally modulated RF transmitter signal. A test instrument is used to measure an overall quality measurement for the transmitter signal as well as individual contributions by each transmitter parameter. Each measured parameter is used to modify the ideal transmitter signal, and a quality measure is determined using the quality measurement algorithm. The individual parameter quality measures are compared with the overall quality measurement to determine percentage contribution of each parameter to the overall quality measurement. From the percentage contribution an operator may understand what is causing problems in the transmitter signal when the overall quality measurement is out of limits.

Abstract: A digital storage oscilloscope includes a source of two or more input signals and a display device. An alternate triggering mechanism includes a selector for selecting one of the input signals. A trigger circuit is responsive to the selected input signal, and generates a trigger signal when a trigger condition is satisfied. A raster signal generator includes a plurality of waveform memories each associated with a respective input signal and responsive to the trigger signal for storing data representing the selected input signal in the waveform memory associated with the selected input signal. The raster signal generator generates a raster image signal representing the selected input signal.

Abstract: An operational amplifier oscillator uses an operational amplifier as a low impedance driver for a resonator, the output from the operational amplifier being a voltage signal at the desired frequency. The operational amplifier has positive and negative feedback paths, with the negative feedback path having a first resistor for driving the impedance at the negative input to a small value when the voltage signal is near a zero crossing and an anti-parallel diode limiter in parallel with the first resistor with an optional series second resistor for driving the impedance at the negative input even smaller when the voltage signal swings away from zero. The positive feedback loop includes a series diode limiter or optional voltage divider. Phase noise is minimized by coupling a filter between the output and the positive feedback path to block the low frequency noise from the positive input of the amplifier.

Abstract: In a logic analyzer or similar binary signal-analyzing instrument, hardware circuitry, such as an ASIC, or other dedicated hardware, is used to perform waveform compression and summarization more rapidly than it could be done by software alone. The hardware is used to perform the compression of the data and to summarize its behavior for visual display. In one embodiment, the hardware starts from a given memory address and compares current timestamp values with final timestamp values to determine the length of the timeslice. Within the timeslice, all of the data is compared to determine whether it remains the same throughout the timeslice or whether it changes. The same approach can be used on violation data, such as glitches and setup and hold violations.

Abstract: An electronic interconnect adapter for a bulkhead mounted high speed coaxial interconnect has a rotatable coupling bushing with a central bore. One side of the bushing has an axially extending flange disposed around the bore with the flange having a threaded interior surface that threadably mates with a threaded exterior surface of the female side of the coaxial interconnect. The opposite side of the bushing has an axially disposed cavity with a diameter greater than the central bore forming a shoulder within the cavity. A male side of the interconnect has a flange radially extending from a shield contact with a mating member extending through bore. A radial slot is formed in the cavity adjacent to the shoulder that receives a retaining member that captures the flange between the shoulder and the retaining member to secure the male side of the high speed coaxial interconnect to the coupling bushing.

Abstract: A replaceable probe tip holder for an associated low capacitance probe head has a cap with a series of cavities formed therein and a bore extending from the inter most cavity to the front end of the cap. A first cavity receives the probe head tubular housing, a second cavity receives a portion of the probe head substrate extending from the housing, and a third cavity receives a first resilient compression member and a first electrically conductive probing tip having a shank and a head. The head is disposed in the third cavity in contact with the first resilient compression member and shank extends through the bore with the end of the shank extending from the front end of the cap. Attachment arms extend from the back end of the cap and are positionable on the outside of the housing. The replaceable probe tip holder may also be configured with differential probing tips having two electrically conductive probing tips extending from the cap.

Abstract: An audio signal control system has a fader control, a memory store, a CPU controlling operation of the memory store and outputting signals to a digital signal processor and thence, via a DAC to a speaker. The invention produces plural sequences of control parameters indicative of the position of the fader and an identifier code representative of each sequence is stored in memory to produce a first version. When a user modifies the position of the fader so a sequence or sequences are modified and a second version of identifier code for the sequences is produced comprising the first version plus the modified sequence. With such a procedure, it is possible for a user to undo/redo versions of the fader control positions and thereby manipulate an audio signal.

Abstract: A method and apparatus for probing a terminal of a ball grid array device, or a conductor of an array of closely-spaced conductors, preferably employs a buried tip resistor located substantially adjacent to the point to be monitored. In this way, a relatively short stub is provided from the connection point to the tip resistor. A receiver amplifier arrangement substantially eliminates an offset error affecting prior art amplifier arrangements, where the offset error is introduced into the signal to be measured due to variation in the resistance value of the tip resistor. It is recognized that the invention is not limited to buried-resistor applications, but is also applicable in probing situations involving the use of tip resistors having a tolerance range greater than 1%.

Abstract: A circuit for acquiring a differential signal and a single-ended signal from a differential signal bus generates a differential output strobe signal and a single-ended strobe signal. A differential amplifier, first and second single-ended amplifiers, and a logic circuit cooperate to produce a digital logic output signal that exhibits an active edge that always occurs later in time than an active edge of the differential output strobe signal.