Abstract: Fast data patterns with desired edge positions are provided. A pattern generator (PG) circuit 10 stores and provides data patterns and respective position control data. A delay circuit 16 delays a clock CLK to produce a position control clock according to the position control data. An output flip flop 18 provides the data patterns following to the position control clock. The position of the clock is controlled as an operation reference of the data pattern and, as a result, controls the edge positions of the output data pattern.

Abstract: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories, parallel to serial converters and DACs respectively. A phase comparator 24 compares data reading clocks from the signal generation blocks 10 and 12 to produce a phase difference signal wherein the data reading clocks are used to read waveform data from the memories within the signal generation blocks 10 and 12. A CPU controls the clock phase shift circuits 26 and 28 according to the phase difference signal to shift phases of the clocks provided to the signal generation blocks 10 and 12 and then makes phase relationship between the output signals of the first and second channels 20 and 22 as desired.

Abstract: This invention relates to a system and method of monitoring, by establishing end to end loopback testing across one or more networks with dissimilar transport technologies. The system allows for connection in loopback mode from a standard interface on a test device to a media adaptor located on an IP-based access network, such as a standard multimedia terminal adapter (“MTA”). End-to-End Quality of service delivered over the transmit and receive path can thus be monitored. Loopback tests are initiated from designated endpoints on the network and made operational by attaching a tag to a telephone number, to allow the gateway to signal connection mode to a call agent.

Abstract: A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I1 and I2 to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.

Abstract: A pulse delay circuit induces lager jitter to faster input reference pulse trains than before. A buffer receives a reference pulse train and provides non-inverted and inverted pulses. Low pass filters (LPF) and comparators receive the non-inverted and inverted pulses from the buffer and provide pulses having delayed leading and trailing edges. Dividers divide the delayed pulses by 2 to produce the respective pulse trains having a half frequency. An XOR gate produces an exclusive OR of the delayed and divided pulse trains to provide a pulse train having delayed leading and/or trailing edges relative to the reference pulse train. If the delays by the LPFs and comparators are changed, the output pulses from the XOR gate have jitter.

Abstract: Delays induced to leading and trailing edges of an input pulse train are updated faster than before. First and second delay paths receive delay data for inducing delays to leading edges and/or trailing edges of an input pulse train. An OR circuit combines the outputs of the delay paths. First and second gates receive the input pulse train and selectively provide the input pulse train to the first and second delay paths independent of the edge position of the input pulse train. A delay time setup circuit generates a CTRL signal for controlling the first and second gates and the loading of the delay data to the first and second delay path. The CTRL signal causes the gates to selectively switch the input pulse train from one delay path to another while the delay data is selectively loaded in the delay path not receiving the input pulse train.

Abstract: A method for the dynamic control of the channel use of a transmission channel as well as a load generator for sending a test sequence generates the test sequence with several test patterns in accordance with a communication protocol to be used for transmission, preferably using a text editor and fixed definitions. A target channel use is defined. Then a predeterminable number of test patterns from the test sequence are sent and actual channel use is determined. Based on actual channel use a number of filler characters or a waiting time are determined for fixing the target channel use. Then the number of characters are sent or the waiting time is implemented until the next set of test patterns are sent. When all the test patterns of the test sequence have been sent, the transmission is terminated.

Abstract: A first test signal from a test signal source is provided to a spectrum analyzer to produce first measurement data. The test signal source is expressed by a first transfer function G(w) and the spectrum analyzer is expressed by second transfer function F(w). A second test signal is provided to the spectrum analyzer to produce second measurement data where the second test signal is derived from the first test signal by shifting the frequency by a known increment. From the first and second measurement data, the components are the same on G(w) but different on F(w). The G(w) components are cancelled by calculation using the first and second measurement data and then the second transfer function F(w) is evaluated independently of G(w).

Abstract: A method and device for analyzing data, the sequence of which is describable by a state machine, has a configurable filter into which the data is input, an emulation of a part of the state machine implemented as a loadable hardware circuit in which states and conditions related to a current state are loaded, and means for determining a new current state from the states in the emulation resulting from applying the conditions to the filtered data. The configurable filter is reconfigured and the loadable hardware circuit is reloaded based upon the new current state being the current state. The process is continued until the data is processed according to the state machine.

Abstract: A jitter inducing circuit receives a reference pulse train and induces desired amounts of jitter to the rising and/or falling edges of the pulses. First and second delay blocks 16 and 18 alternately delay the selected edge or edges of the provided reference pulse train interval by preset delay times for every interval. A signal composer 46 composes the outputs of the first and second delay blocks 16 and 18. A delay time setup circuit controls the delay times of the delay blocks 16 and 18. The delay times may change for each interval as a function of time so as to trace a desired function such as a sinusoidal or triangular function.

Abstract: A method and device for finding a reference pattern in a serial stream of digital data draws up comparison tables for the front and rear bits of the reference pattern. Using the comparison table for the front bits, bits which in terms of time are located upstream of a point P in the data stream are compared, and using the comparison table for the rear bits, bits which in terms of time are located downstream of point P in the data stream are compared. Next, the number of bits matching the reference pattern upstream and downstream of the point P are added up, and in case the sum total is greater than or equal to the number of bits in the reference pattern, there is a signal that the reference pattern has been found.

Abstract: A device for analyzing digital data formulated in accordance with a communication protocol has a data memory for storing digital data to be analyzed. A microcode memory stores a microcode that represents at least part of the communication protocol. A data register is loaded with a pre-determined number of bits from the data memory, and a microcode register is loaded with a pre-determined number of bits from the microcode memory. The content of the microcode register is used to analyze the content of the data register. The results of the analysis are stored in an output memory. An addressing unit for the data memory and another addressing unit for the microcode memory take into account the contents of the data and/or microcode registers in determining the corresponding addresses.

Abstract: A method of multi-protocol call trace on GPRS Gb and Gr interfaces of a GSM network uses distributed processing. Probes are situated at locations where measurements are desired in a monitored mobile network, such as at Gb and Gr interfaces, and are connected in a non-intrusive manner to the mobile network. A remote server is coupled to each probe over a local area network (LAN) to process data as it is acquired by the probe. The probe and remote server are coupled to a central server via a wide area network (WAN), as are client servers. The remote servers manage the probe data (packet data units—PDUs) in real time to create appropriate transactional and raw data indices that are stored locally with the PDUs. Call/procedure trace applications are initiated from the client servers and disseminated by the central server to the remote servers.

Abstract: A digital counter with a dial position having a hardware part which determines the n lowest-value bits of the dial position and a software part which determines the remaining higher-value bits of the dial position includes first and a second software parts as the software part with the dial position being a combination of the first software part and the hardware part when the hardware part is in a first counting range, and being a combination of the second software part and the hardware part when the hardware part is in a second counting range.

Abstract: A method for emulating a terminal for testing a telecommunication network has the terminal being assigned a user interface programmable by a user for executing a communication sequence, the programming of the user interface having first of all the provisioning of a multitude of keywords from which the communication sequence for the terminal is compiled, a program code being correlated with each keyword. Moreover, an entry mask on a display device is provided into which the user enters a series of at least two keywords for compiling the communication sequence. Finally, the program codes that are correlated with the keywords entered into the entry mask by the user are linked to give an executable program. A test apparatus for testing the telecommunication network has a storage device in which the keywords are filed and from which the communication sequence is compiled for participation in the communication, with the program code being correlated with each keyword.

Abstract: A keyboard with a supporting device that rotates from a folded state to an unfolded state includes a housing for receiving the supporting device in the folded state such that the supporting device unfolds from the keyboard top about an angle greater than 270 degrees to the unfolded state to support the keyboard. The supporting device includes a slit-shaped contour having a curved region for riding on an interior surface of the keyboard bottom within the housing when moving between the folded and unfolded states and having a linear region to form a slit with the curved region for self-locking with the keyboard bottom in the unfolded state. When in the folded state the supporting device does not protrude above the keyboard top or beyond the keyboard edge, and provides an aesthetic exterior when attached to an information processing device in a transport mode.

Abstract: The present invention relates to an assembly with a base board and at least one daughter board, which base board includes at least a first attachment means for attaching the base board to a mainframe, with the front of the assembly which remains accessible from the exterior after installation of the assembly in the mainframe being of a standardized width, the daughter board being connected to the base board via at least a second attachment means in such a way that an electrically conductive front panel of the daughter board forms at least a portion of the front of the assembly, with at least a portion of the front panel of the daughter board being of the standardized width.

Abstract: A circuit for variably delaying a serial digital data signal delays a parallel data clock rather than the serial digital data signal directly. A delay circuit receives the parallel data clock to provide a delayed parallel data clock, the delay being a function of a control signal. A phase-locked loop receives the delayed parallel data clock to generate a serial data clock in phase with the delayed parallel data clock. A parallel-to-serial converter reads an n-bit parallel digital data signal from a memory using the delayed parallel data clock, and converts the parallel digital data signal to the serial digital data signal using the serial data clock. By changing the control signal continuously, the delay of the delayed parallel data clock and of the serial digital data signal also changes continuously so the serial digital data signal appears to have jitter.

Abstract: A method and device for analyzing data reads unstructured data into a data memory and compares it with a structure description contained in a structure description memory to identify components of the unstructured data. An addressing logic is initiated in accordance with the identified components of the unstructured data. A register is coupled to the addressing logic to serve as an interface for access to the unstructured data based on the identified components.