Abstract: This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.

Abstract: Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 ?m) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.

Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

Abstract: In an up-converter path of a transmitter, wide-band signal system like direct. conversion WiGig, a high pass filter (HPF) is placed in the baseband path after the low pass filter (LPF) but before the mixers. The baseband signal of WiGig can have a bandwidth of 800 MHz. The HPF removes the frequencies from 0-40 MHz from the baseband signal and degrades the overall signal of the baseband by a dB or so. However, the frequency pulling is significantly reduced since oscillator frequency and Radio frequency (RF) transmitter frequencies after conversion become further separated when compared a system using to the conventional approach. This causes the injected signal to fall outside the locking range of the oscillator. The concern of substrate coupling is reduced and allows for a reduction in the physical distance between the oscillator and the mixer and reduces a shift in the desired target frequency of operation.

Abstract: A large gain is used to start up the oscillation of the crystal quickly. Once the oscillation starts, the amplitude is detected. A control circuit determines based on the measured amplitude to disable a low resistance path in the controlled switch array to reduce the applied gain below the power dissipation specification of the crystal. Another technique introduces a mixed-signal controlled power supply multi-path resistive array which tailors the maximum current to the crystal. A successive approximation register converts the amplitude into several partitions and enables/disables one of several power routing paths to the inverter of the oscillator. This allows a better match between the crystal selected by the customer and the on-chip drive circuitry to power up the oscillator without stressing the crystal. The “l/f” noise of the oscillator circuit is minimized by operating transistors in the triode region instead of the linear region.

Abstract: Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their complements and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

Abstract: The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna.

Abstract: Transceiver calibration is a critical issue for proper transceiver operation. The transceiver comprises at least one RF transmit chain and one RF receive chain. A closed loop path is formed from the digital block, the RF transmit chain, the substrate coupling, the RF receive chain back to the digital block and is used to estimate and calibrate the transceiver parameters over the operating range of frequencies. The substrate coupling eliminates the need for the additional circuitry saving area, power, and performance. In place of the additional circuitry, the digital block which performs baseband operations can be reconfigured into a software or/and hardware mode to calibrate the transceiver. The digital block comprises a processor and memory and is coupled to the front end of the RF transmit chain and the tail end of the RF receive chain.

Abstract: One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function: thereby providing two simultaneous operations being determined in place of the one differential function.

Abstract: A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

Abstract: A large gain is used to start up the oscillation of the crystal quickly. Once the oscillation starts, the amplitude is detected. A control circuit determines based on the measured amplitude to disable a low resistance path in the controlled switch array to reduce the applied gain below the power dissipation specification of the crystal. Another technique introduces a mixed-signal controlled power supply multi-path resistive array which tailors the maximum current to the crystal. A successive approximation register converts the amplitude into several partitions and enables/disables one of several power routing paths to the inverter of the oscillator. This allows a better match between the crystal selected by the customer and the on-chip drive circuitry to power up the oscillator without stressing the crystal. The “l/f” noise of the oscillator circuit is minimized by operating transistors in the triode region instead of the linear region.

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract: A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.

Abstract: The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators, instead of having extra dummy fingers, are also aligned right next to each other to minimize the mismatching layout effect.

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Abstract: Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 ?m) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.

Abstract: The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna.

Abstract: Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.