Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: A design for test focused tester has a single printed circuit board tester architecture. By focusing on design for test testing and eliminating functional testing, the design for test focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.

Abstract: A modular tester architecture allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module, networking interface modules, a controller module, a current measurement module, and a DC parametrics module, among others.

Abstract: A scan test viewing and analysis tool for an integrated circuit tester provides inter-related views of scan tests on an integrated circuit device. The tool processes a test program specification, execution results and device definition to produce cross-referencing data, which the tool then uses to provide navigation links between correlated locations in a cyclized test view, procedural test program view, and views of signal vectors, scan state and scan vectors. The tool also provides a capability to edit the test program in the views.

Abstract: A modular tester architecture allows end-users to mix-and-match scan chain modules and clock driver modules. Modules are interconnected via a synchronization bus allowing the test modules to synchronize with each other so that each can perform its portion of the overall test at the proper time in relation to the testing performed by other modules. The modules can include a BIST driver module, a data acquisition module, networking interface modules, a controller module, a current measurement module, and a DC parametrics module, among others.

Abstract: A scan test viewing and analysis tool for an integrated circuit tester provides inter-related views of scan tests on an integrated circuit device. The tool processes a test program specification, execution results and device definition to produce cross-referencing data, which the tool then uses to provide navigation links between correlated locations in a cyclized test view, procedural test program view, and views of signal vectors, scan state and scan vectors. The tool also provides a capability to edit the test program in the views.

Abstract: A DFT-focused tester has a single printed circuit board tester architecture. By focusing on DFT testing and eliminating functional testing, the DFT-focused tester reduces or eliminates requirements for high speed, precision signal formatting and timing circuitry that require a multiple board architecture interconnected via a high speed backplane. The single board architecture places a vector sequencer and vector memory close to the device under test, which provides short, consistent signal paths to the device and eliminates the need for dead cycles and synchronization between tester boards.