Patents Assigned to Tessera Interconnect Materials, Inc.
  • Patent number: 7342802
    Abstract: To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an interlayer insulating film allows for interlayer connection between plural wiring films insulated from one another with plural interlayer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the interlayer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 ?m or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: March 11, 2008
    Assignee: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Yoshitaka Fukuoka
  • Publication number: 20070221329
    Abstract: An apparatus and method are provided for processing an item by distributing a liquid onto a surface of the item. The apparatus includes a conveyor which defines an undulating path which varies in vertical position relative to the direction of movement of the item conveyable along the path. Thus, the path has at least one apex at a location of the path higher than other locations in the direction of movement along the path. A sprayer is operable to spray the liquid onto the surface of the item at a location that is substantially aligned to the apex of the path.
    Type: Application
    Filed: October 23, 2006
    Publication date: September 27, 2007
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Kazuo Sakuma, Inetaro Kurosawa, Kiyoshi Hyodo
  • Patent number: 7238603
    Abstract: A connecting member between wiring films is provided in which: a normal copper foil, which is a general-purpose component and not expensive, or the like can be used as a material; formation of bumps is sufficiently achieved by conducting etching one time; and a necessary number of layers can be laminated and pressed collectively at a time. Bumps, which are formed approximately in a cone-shape, for connecting wiring films of a multilayer wiring substrate are embedded in a second resin film that serves as an interlayer insulating film.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: July 3, 2007
    Assignee: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Kimitaka Endo
  • Publication number: 20070121305
    Abstract: A multilayer wiring board includes a first insulating film and a first patterned metal wiring film extending along a first major surface thereof, and a second insulating film a second patterned metal wiring film extending along a second major surface thereof. The wiring board includes solid metal interconnects connecting the first patterned metal wiring film to the second patterned metal wiring film, the interconnects extending through at least one of the first and second insulating films, and a microelectronic element disposed between the first and second patterned wiring films, the microelectronic element having bond pads conductively connected to the first patterned metal wiring films. The wiring board also includes a plurality of external contacts exposed at one or more external surfaces of the multilayer wiring board, the contacts being conductively connected to at least one of the first and second patterned metal wiring films.
    Type: Application
    Filed: January 24, 2007
    Publication date: May 31, 2007
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Yoshitaka Fukuoka
  • Publication number: 20060258139
    Abstract: A method of making a microelectronic element includes making a connection component by providing a metal layer having a top surface and a bottom surface, providing a dielectric layer over the top surface of the metal layer and forming openings in the dielectric layer to expose portions of the top surface of the metal layer. The method includes providing conductive elements atop the dielectric layer, at least some of the conductive elements extending through the openings in the dielectric layer and being in contact with the metal layer, and plating first conductive protrusions atop the at least some of the conductive elements extending through the openings in the dielectric layer, the first conductive protrusions extending away from the metal layer. The method includes selectively removing portions of the metal layer from the bottom surface of the metal layer to form second conductive protrusions that extend away from the first conductive protrusions.
    Type: Application
    Filed: July 17, 2006
    Publication date: November 16, 2006
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Masayuki Ohsawa
  • Patent number: 7096578
    Abstract: A method is provided for manufacturing a multi-layer wiring circuit substrate. A first metal layer is selectively etched in first areas to reduce a thickness of the metal layer in the first areas and to form protrusions in other areas which extend above the etched areas. An interlayer-insulating layer is formed to overlie the etched areas of the first metal layer. The interlayer-insulating layer has an inner surface which confronts the etched first areas and an outer surface remote from the inner surface, such that the protrusions extend through the interlayer-insulating layer and have ends exposed at the outer surface. A second metal layer is then provided in conductive communication with the exposed ends of the protrusions, and the first and second metal layers are selectively patterned from surfaces remote from the interlayer-insulating layer.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: August 29, 2006
    Assignee: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Masayuki Ohsawa