Patents Assigned to Tesserae Technologies
  • Publication number: 20110013044
    Abstract: Within a digital acquisition device with a built in flash unit, the exposure of an acquired digital image is perfected using face detection in the acquired image is provided. Groups of pixels that correspond to plural images of faces are identified within a digitally acquired image, and corresponding image attributes to the group of pixels are determined. An analysis is performed of the corresponding attributes of the groups of pixels. It is then determined to activate the built-in flash unit based on the analysis. An intensity of the built-in flash unit is determined based on the analysis. Alternatively based on similar analysis, a digital simulation of the fill flash is performed on the image.
    Type: Application
    Filed: September 29, 2010
    Publication date: January 20, 2011
    Applicant: Tessera Technologies Ireland Limited
    Inventors: Eran Steinberg, Peter Corcoran, Petronel Bigioi
  • Patent number: 7868922
    Abstract: An implementation efficient method of distinguishing between foreground and background regions of a digital image of a scene includes capturing two images of nominally the same scene and storing the captured images in DCT-coded format. The first image is taken with the foreground more in focus than the background and the second image is taken with the background more in focus than the foreground. Regions of the first image are assigned as foreground or background according to whether the sum of selected higher order DCT coefficients decreases or increases for the equivalent regions of the second image.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: January 11, 2011
    Assignee: Tessera Technologies Ireland Limited
    Inventors: Mihai Ciuc, Adrian Zamfir, Adrian Capata, Peter Corcoran, Eran Steinberg
  • Patent number: 7869628
    Abstract: An image acquisition device includes a first speed-optimized filter for producing a first set of candidate red-eye regions for an acquired image; and a second analysis-optimized filter for operating on the first set of candidate red eye regions and the acquired image.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 11, 2011
    Assignee: Tessera Technologies Ireland Limited
    Inventors: Peter Corcoran, Eran Steinberg, Alexei Pososin, Mihai Ciuc
  • Patent number: 7865036
    Abstract: A method for digital image eye artifact detection and correction include identifying one or more candidate red-eye defect regions in an acquired image. For one or more candidate red-eye regions, a seed pixels and/or a region of pixels having a high intensity value in the vicinity of the candidate red-eye region is identified. The shape, roundness or other eye-related characteristic of a combined hybrid region including the candidate red-eye region and the region of high intensity pixels is analyzed. Based on the analysis of the eye-related characteristic of the combined hybrid region, it is determined whether to apply flash artifact correction, including red eye correction of the candidate red-eye region and/or correction of the region of high intensity pixels.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: January 4, 2011
    Assignee: Tessera Technologies Ireland Limited
    Inventors: Mihai Ciuc, Adrian Capata, Florin Nanu, Eran Steinberg, Peter Corcoran
  • Patent number: 7864990
    Abstract: An image processing apparatus for tracking faces in an image stream iteratively receives a new acquired image from the image stream, the image potentially including one or more face regions. The acquired image is sub-sampled (112) at a specified resolution to provide a sub-sampled image. An integral image is then calculated for a least a portion of the sub-sampled image. Fixed size face detection (20) is applied to at least a portion of the integral image to provide a set of candidate face regions. Responsive to the set of candidate face regions produced and any previously detected candidate face regions, the resolution at which a next acquired image is sub-sampled is adjusted.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 4, 2011
    Assignee: Tessera Technologies Ireland Limited
    Inventors: Peter Corcoran, Alexandru Drimbarean, Alexei Pososin, Petronel Bigioi, Eran Steinberg, Stefan Petrescu, Florin Nanu
  • Publication number: 20100323475
    Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.
    Type: Application
    Filed: August 20, 2010
    Publication date: December 23, 2010
    Applicant: Tessera Technologies Hungary Kft..
    Inventor: Avner Badehi
  • Patent number: 7853043
    Abstract: A method of processing a digital image using face detection within the image achieves one or more desired image processing parameters. A group of pixels is identified that correspond to an image of a face within the digital image. Default values are determined of one or more parameters of at least some portion of the digital image. Values are adjusted of the one or more parameters within the digitally-detected image based upon an analysis of the digital image including the image of the face and the default values.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: December 14, 2010
    Assignee: Tessera Technologies Ireland Limited
    Inventors: Eran Steinberg, Yury Prilutsky, Peter Corcoran, Petronel Bigioi
  • Patent number: 7844135
    Abstract: A method of automatically establishing the correct orientation of an image using facial information. This method is based on the exploitation of the inherent property of image recognition algorithms in general and face detection in particular, where the recognition is based on criteria that is highly orientation sensitive. By applying a detection algorithm to images in various orientations, or alternatively by rotating the classifiers, and comparing the number of successful faces that are detected in each orientation, one may conclude as to the most likely correct orientation. Such method can be implemented as an automated method or a semi automatic method to guide users in viewing, capturing or printing of images.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: November 30, 2010
    Assignee: Tessera Technologies Ireland Limited
    Inventors: Eran Steinberg, Yury Prilutsky, Peter Corcoran, Petronel Bigioi, Leo Blonk, Mihnea Gangea, Constantin Vertan
  • Patent number: 7807508
    Abstract: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts on the rear surface. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: October 5, 2010
    Assignee: Tessera Technologies Hungary Kft.
    Inventors: Vage Oganesian, Andrey Grinman, Charles Rosenstein, Felix Hazanovich, David Ovrutsky, Avi Dayan, Yulia Aksenton, Ilya Hecht
  • Patent number: 7781240
    Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: August 24, 2010
    Assignee: Tessera Technologies Hungary Kft.
    Inventor: Avner Badehi
  • Publication number: 20100040844
    Abstract: A system and method for decorative elements having multiple visual appearances. The decorative elements may present different colors and/or other visual appearance characteristics and yet function as a durable construction material, like a traditional brick, tile or shingle. The decorative elements may receive a mechanical operation that permanently physically alters the decorative element, such as a cutting, sawing, drilling or molding operation, while the decorative element is functional to provide a controllable visual appearance both before and after the physical alteration. The decorative elements may be autonomous in that power needed to change visual appearance states can be gathered by an integrated energy harvesting device, such as a solar cell. A color chip system may be used to select decorative element features.
    Type: Application
    Filed: October 23, 2009
    Publication date: February 18, 2010
    Applicant: Tesserae Technologies
    Inventor: Erik Larson
  • Patent number: 7642629
    Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: January 5, 2010
    Assignee: Tessera Technologies Hungary Kft.
    Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
  • Patent number: 7495341
    Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: February 24, 2009
    Assignee: Tessera Technologies Hungary Kft.
    Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
  • Patent number: 7479398
    Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: January 20, 2009
    Assignee: Tessera Technologies Hungary Kft.
    Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
  • Patent number: 7408249
    Abstract: A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 5, 2008
    Assignee: Tessera Technologies Hungary Kft.
    Inventor: Avner Badihi
  • Publication number: 20080150121
    Abstract: A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 26, 2008
    Applicant: Tessera Technologies Hungary Kft.
    Inventors: Vage Oganesian, Guilian Gao, Belgacem Haba, David Ovrutsky
  • Publication number: 20080099907
    Abstract: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts on the rear surface. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.
    Type: Application
    Filed: April 25, 2007
    Publication date: May 1, 2008
    Applicant: Tessera Technologies Hungary Kft.
    Inventors: Vage Oganesian, Andrey Grinman, Charles Rosenstein, Felix Hazanovich, David Ovrutsky, Avi Dayan, Yulia Aksenton, Ilya Hecht
  • Publication number: 20080099900
    Abstract: A method is provided for fabricating a unit including a semiconductor element such as a sensor unit, e.g., for optical imaging. A semiconductor element has plurality of conductive features exposed at the front surface and semiconductive or conductive material exposed at least one of the front and rear surfaces. At least some of the conductive features are insulated from the exposed semiconductive or conductive material. By electrodeposition, an insulative layer is formed to overlie the at least one of exposed semiconductive material or conductive material. Subsequently, a plurality of conductive contacts and a plurality of conductive traces are formed overlying the electrodeposited insulative layer, the conductive traces connecting the conductive features to the conductive contacts. The unit can be incorporated in a camera module having an optical element in registration with an imaging area of the semiconductor element.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: Tessera Technologies Hungary Kft.
    Inventors: Vage Oganesian, David Ovrutsky, Charles Rosenstein, Belgacem Haba, Giles Humpston
  • Publication number: 20080017879
    Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
    Type: Application
    Filed: August 21, 2007
    Publication date: January 24, 2008
    Applicant: Tessera Technologies Hungary Kft.
    Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
  • Publication number: 20080012115
    Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
    Type: Application
    Filed: August 13, 2007
    Publication date: January 17, 2008
    Applicant: Tessera Technologies Hungary Kft.
    Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian