Abstract: Testing of a mixed signal integrated circuit (IC) potentially in the form of a die using a tested/calibrated integrated circuit. In an embodiment, the mixed signal IC generates an analog signal from a symbol, and transmits the analog signal to the calibrated integrated circuit. The calibrated IC determines a valid symbol corresponding to the signal level (e.g., voltage) of the received analog signal, and determines a deviation of the signal level of the received analog signal from the voltage level corresponding to the valid symbol. The deviation is deemed to represent the degree of defect of the mixed signal IC based on the assumption that the calibrated IC operates accurately. The deviation is used to either discard or qualify/accept the mixed signal IC.

Abstract: An integrated oxide removal and processing system (10) includes a process module (30) that may intentionally add at least one film layer to a single semiconductor wafer (32). The integrated oxide removal and processing system (10) also includes a transfer chamber module (20) used to align the semiconductor wafer (32) for the process module (30). The transfer chamber module (20) may expose the semiconductor wafer (32) to a vaporous solution that is inert with respect to the semiconductor wafer (32) and operable to remove an oxide layer (110) therefrom. More specifically, the semiconductor wafer (32) includes silicon. In a further embodiment, the vaporous solution includes HF. In yet a further embodiment, the vaporous solution includes 0.049% to 49% HF.

Abstract: Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge, wherein the protection device is interdigitated with the component. The invention is applicable to many kinds of components, for example to a noise-decoupling capacitor shaped as an nMOS transistor with thin dielectric, or to an input buffer shaped as an nMOS transistor, or to an antenna shaped as an nMOS transistor. The protection device includes an nMOS transistor. The insulator of the gates, preferably silicon dioxide, is thin and in need of protection against ESD damage. The interdigitation may be configured in one or more planes. Further, the protection device may lie in a single plane spaced apart from the plane defined by the components. The protection device may also partially be merged with the component.

Abstract: A system provides primary and alternate control circuits to a controlled system through an output port. A monitoring circuit that monitors a parameter of the controlled system selects the control methodology. The primary control circuit, consisting of a primary active part and a regulator, and an alternate control circuit receive feedback from the controlled system. A switching mechanism, controlled by an output of the monitoring circuit, connects the appropriate control circuit to the controlled system and switches internal connections as needed. During alternate mode, a simulator of the controlled system as driven by the primary active control circuit provides an output representative of the output of the regulator that would cause the current output of the controlled system if the system were in primary mode. This simulator output is used when transitioning back to primary mode to minimize transients in the output of the controlled system.

Abstract: Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.

Abstract: By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can be counted. After decoding this count information, it can be used with the initial and final state metric values from the decoder to compute the desired full path metric. The method only requires monitoring state metric wrap-arounds moving in one direction and hence only needs to increment the extra counter as opposed to having to do likewise in the opposite direction. In another embodiment, the method can handle both forward and backward progressions by incrementing and decrementing a counter.

Abstract: To apply a desired voltage at a node driving a load impedance, a voltage source providing the desired voltage is connected to the node. In addition, a current source supplying an amount of current that would be drawn by the impedance if the voltage source alone were connected across the impedance. As a result, the voltage source may be freed substantially from supplying current, which may be advantageously used in several situations. For example, the approach can be used to connect a voltage source directly to a high load without potentially requiring a buffer between the voltage source and the node. Alternatively, the approach can be used to apply the same desired voltage at each of multiple nodes connected in series using the same voltage source without being affected by the routing resistance generally present between each pair of the nodes.

Abstract: The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.

Abstract: An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.

Abstract: A filter comprises a tap multiplication circuit and a tap digital-to-analog (“DAC”) unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that, permit one tap multiplication to be output while another tap multiplication is being computed for a 1/N rate implementation.

Abstract: A method, and associated storage medium containing software and a system, comprises extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.

Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

Abstract: A system and method is provided for processing four samples per clock period of an orthogonal frequency division multiplex symbol 10 having a length not a multiple of four. The method includes providing a sequence of data samples 12 and a sequence of non-data samples 14 and 16. The method includes selecting four input samples from one of the data samples 12 and the non-data samples 14 and 16 based on a clock signal. The method includes storing at least a portion of contents of a first group of memory cells 112 in a second group of memory cells 116. The first group of memory cells 112 comprised of four memory cells 112a-d. The method also provides for storing the selected four input samples in the first group of memory cells 112.

Abstract: In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that implements a first data packet, and one or more devices configurable to communicate according to a second protocol that implements a second data packet having a predetermined quadrature component. The one or more devices configurable to communicate according to the second protocol associate detection of the predetermined quadrature component with a function that is not supported by the one or more devices that communicate according to the first protocol.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor. That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: A low noise multi-loop radio frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune PLL and a coarse tune PLL. The fine tune PLL outputs a fine tune signal with a frequency fR?P, P beings an integer, while the coarse tune PLL outputs a coarse tune signal with frequency fR?A, where A is an integer. A translation PLL has a unity multiplication factor and is driven by the fine tune signal output. The frequency synthesizer has a Gilbert cell double balanced mixer coupled between the coarse tune and the translation PLLs, the Gilbert cell mixer combining the coarse tune signal and the output signal of the translation PLL and coupling the mixed signal into the translation PLL. The translation loop outputs a signal with a frequency proportional to the linear sum of the coarse tune signal and the fine tune signal.

Abstract: A wireless communication network comprising a wireless receiver. The wireless receiver comprises at least a first antenna for receiving packets, wherein each of the received packets comprises a plurality of bits and each of the plurality of bits is modulated by a frequency offset. The wireless receiver also comprises circuitry for cycling through a hopping sequence, wherein the hopping sequence comprises a sequence of frequency bands and circuitry for demodulating each received packet in response to a frequency band in the hopping sequence. The wireless receiver also comprises circuitry for detecting the frequency offset of each of the plurality of bits and converting the frequency offset of each of the plurality of bits into a corresponding DC voltage for each of the plurality of bits.

Abstract: The present invention discloses a circuit (10) adapted to compensate for RMR variations and shunt resistance across the RMR comprising a first current source (idc1) coupled to a first resistor (r1), a second current source (idc2) coupled to a second resistor (r2), wherein the first resistor (r1) and the second resistor (r2) are coupled, a resistive sensor (RMR) coupled on either side to a third resistor (r3) and to a fourth resistor (r4), and a transconductance feedback block (GM) coupled to the resistive sensor (RMR), the third resistor (r3), and to the fourth resistor (r4).

Abstract: A method of detecting endpoint of a plasma etching system that measures the DC voltage drop across both the sheath and the film being etched. When the film is nearly removed, a drop in voltage indicates thinning of the film which detects endpoint for etching before optical emission techniques. The voltage drop is measured across resistors within the matching network.

Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.