Abstract: Method and apparatus for high resolution tracking via mono-pulse beam-forming in a communication system in which the capacity and range of mobile or fixed wireless communication base stations are improved by implementing a single or multiple antenna beam per signal path. Adaptive beam-forming based on up-link direction-of arrival estimation can be performed without using the above-mentioned computationally intensive techniques.

Abstract: Improved long gas injectors for a vertical furnace used in semiconductor wafer processing are useful to minimize particulate contamination in the wafer processing area of the furnace, and minimize distortion of the long injectors during thermal excursions. The improved injectors are fabricated with a stabilizing quartz standoff positioned near the onset of the vertical portion of the injector tube which adds support to the long tube. Thickness of the standoff is calculated to define and enforce a specified separation distance between liner and injector, as well as to provide dual alignment points at the base of the liner and at the tip of the injector.

Abstract: The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Abstract: Implementation of communication between data processors includes a first task (A) running on a first data processor (11) determining that communication is desired between the first task and a second task (B) running on a second data processor (13). The first data processor interrupts the second data processor if the second task is blocked with respect to communication on a predetermined communication channel. If the second task is not blocked with respect to communication on the predetermined communication channel, the first data processor participates in the desired communication on the predetermined communication channel without interrupting the second data processor.

Abstract: A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.

Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.

Abstract: A circuit takes a reference strobe signal as a first input, and a strobe ready signal generated from a memory that is strobed by the reference strobe signal as a second input. The circuit generates a self-timed strobe signal along with other control signals that are used to perform a subsequent memory access in a single clock cycle, thereby doubling memory access bandwidth.

Abstract: One aspect of the invention is an amplifier (10), comprising an input stage amplifier (20) coupled to an output node (81). The amplifier (10) further comprises a class D output stage (50), which comprises at least two switching elements (P1, N1) and coupled to the output node (81). The amplifier (10) also comprises a control circuit (40) coupled to the output stage (50). The control circuit (40) is operable to produce a tri-state output of the output stage (50) in response to a sensed value proportional to an amount of current that flows to the output node (81).

Abstract: The present invention provides an apparatus and system for high speed end-to-end telecommunication traffic using an Asynchronous Transfer Mode (ATM) architecture for convergence of video, data and voice in an SOHO application using a DSL router. An ATM processor (120) enables traffic shaping, and operation and maintenance processing within a single module. The ATM processor (120) further includes a processor (114) which executes firmware from a program memory (110). A register block (116) is provided for communicating setup and teardown notification, and OAM configuration to the processor (114) and a connection state RAM (112) provides for communicating connection configuration in which this information is used by the processor (114) when performing the functions of switching, QoS, and OAM. Transmit scheduler hardware (118) is provided for the scheduling of ATM cell transmission and is configured by the processor (114).

Abstract: A method and apparatus for enabling z-axis offset of narrow metal ties straps in lead frames used for packaging integrated circuits to prevent bowing or distortion. Simultaneous offsetting of the tie strap and stress relief mechanisms are provided on both the front and back sides of the lead frame. Those mechanisms include indentations along the long or primary axis of each tie strap, coupled with depressions across the top surface both at the center of the lead frame and between the base of the off set and the chip attach locations to prevent bowing in small pad and no pad lead frames, in particular.

Abstract: Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

Abstract: A processing device (200) includes three hardware extensions: a motion estimation extension 202, a pixel interpolation extension 204 and a DCT/iDCT extension 206. The hardware extensions perform functions which would otherwise be highly processor intensive, resulting in high power consumption and/or low quality video/imaging processing. The processing device 200 could be used, for example, in a mobile videophone 150.

Abstract: A method for reducing the drain resistance of a drain-extended MOS transistor in a semiconductor wafer, while maintaining a high transistor breakdown voltage. The method provides a first well (502) of a first conductivity type, operable as the extension of the transistor drain (501) of the first conductivity type; portions of the well are covered by a first insulator (503) having a first thickness. A second well (504) of the opposite conductivity type is intended to contain the transistor source (506) of the first conductivity type; portions of the second well are covered by a second insulator (507) thinner than the first insulator. The first and second wells form a junction (505) that terminates at the second insulator (530a, 530b). The method deposits a photoresist layer (510) over the wafer, which is patterned by opening a window (510a) that extends from the drain to the junction termination.

Abstract: A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate coupled to respond to an input signal on an input(9), an N-channel pulldown transistor (M1) having a drain coupled to the output, a source coupled to ground, and a gate coupled to respond to the input signal. A first N-channel transistor (M2) has a drain coupled to a gate of the output transistor and the supply voltage by means of a current source (8) and a source coupled to ground by means of a second current source (13). A first diode-connected N-channel transistor (M3), a second diode-connected N-channel transistor (M4), and a first level shifting circuit (17) are coupled in series between ground and a gate of the N-channel transistor, and a current source (7) is coupled between the first supply voltage and the gate of the first N-channel transistor.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: A retry algorithm determines the maximum number of transmissions and retransmissions that may be attempted for the frame in the head of a transmit queue or transmit buffer that needs to be transmitted across a communications link. The algorithm attempts to achieve a constant delay for each packet in frame by taking into account the number of frames residing in the transmit queue, the number of transmit opportunities elapsed between the arrivals of two successive frames in the transmit queue s, as well as the buffering capabilities of both the transmitting and receiving sides. The transmission and retransmission control technique provides for a way of managing the TX and RX buffers with a size that is suitable for the application being used and the underlying transport network. The number of retries is adapted to incoming and outgoing data rate changes in order to provide a fixed delay wireless link transport and maximize effective channel utilization.

Abstract: Each of a plurality of nodes in a wireless network is capable of generating, transmitting, and receiving beacons in a distributed fashion. Each beacon contains information regarding the order of which other nodes are to transmit beacons and wireless medium access information as to when various nodes are to access the network. Nodes that are in separate “extended neighborhoods” are permitted to transmit their beacons simultaneously without risking beacon collisions. The beacons contain information that is used to ensure this result. Using the distributed beacon mechanism, each node can reserve access to the wireless medium. In the disclosed embodiments, a central coordinator is not needed.

Abstract: A communication system 10 initialized using an iterative training portion is disclosed. The communication system 10 comprises a first transceiver 12 operable to communicate according to a digital subscriber line standard and a second transceiver 14 operable to communicate according to the digital subscriber line standard with the first transceiver 12. The first and the second transceivers 12, 14 are operable to perform an initialization 50, including a handshake portion 52, a channel analysis portion 56, and a training portion 54, the first and second transceivers 12, 14 negotiating a plurality of iterations of the training portion 54.

Abstract: According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.

Abstract: The present invention provides a method for far branch and call instructions. The present invention includes the link-time modification of object code generated by the compiler or assembler and the addition of custom generated object code to the link for the purpose of implementing far branches and calls without changing the compiler generated instructions or expanding compiler generated object code.