Abstract: A method for providing common-mode feedback is provided. A common-mode current is applied to a common-gate amplifier, and the common-mode current is sensed. In response to the sensed common-mode current, a control voltage is generated. A first feedback current (which is generated in response to the control voltage) can then be applied to differential ground of the common-gate amplifier if the common-mode current is less than a predetermined threshold. Additionally, a second feedback current (which is generated in response to the control voltage) can be applied to input terminals of the common-gate amplifier if the common-mode current is greater than the predetermined threshold.

Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.

Abstract: A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

Abstract: An integrated circuit containing an SRAM array having a strap row. The strap row has a well tap active area that partially overlaps adjacent first polarity wells and a second polarity well that is located between the adjacent first polarity wells. A well contact plug is disposed on a top surface of a tap layer located within the well tap active area.

Abstract: An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

Abstract: A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal.

Abstract: For protecting a speaker, an input signal is received, and an excursion of the speaker that would be caused by the input signal is predicted. In response to the predicted excursion exceeding a threshold, a targeted excursion of the speaker is determined by compressing the predicted excursion. The targeted excursion is translated into an output signal, which is output to the speaker.

Abstract: A system and method for operating an electronic device used in light processing. A method comprises altering a spatial relationship between a spatial light modulator (SLM) and a light incident on the SLM, shifting light modulator states of a first portion of light modulators to a second portion of light modulators, and placing a third portion of light modulators in the SLM into a performance degradation-reducing mode. The amount of shifting performed is proportional to the amount of change in the spatial relationship. The method allows for a change in light modulators used to modulate the light, thereby preventing the overuse of some of the light modulators, which may help to prevent degradation of the light modulators. The performance degradation reducing mode may help to further reduce or even reverse the performance degradation of the light modulators.

Abstract: A method in accordance with an embodiment of the invention includes producing a first signal match indication based on at least one match indication indicative of a match between at least one signal received in at least one band and a reference signal. The method also includes producing a first signal multipath combined signal based upon the first signal match indication, and detecting a first peak in the first multipath combined signal.

Abstract: One embodiment of the invention includes a regulator circuit that regulates a substantially constant magnitude of an output voltage at an output node. The circuit includes a master stage configured to set a first threshold voltage and a second threshold voltage. The first threshold voltage can have a magnitude that is greater than the second threshold voltage. The circuit also includes a charging follower stage configured to conduct a first current from a first power rail to the output node. The first current can increase in response to a transient decrease of the output voltage relative to the first threshold voltage. The circuit further includes a discharging follower stage configured to conduct a second current from the output node to a second power rail. The second current can increase in response to a transient increase of the output voltage relative to the second threshold voltage.

Abstract: A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable foldable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W=>1.

Abstract: Adaptive pulse-width modulated sequences for sequential color display systems and methods. A method for displaying an image comprises receiving the image, computing a duty cycle for the image, generating a color sequence based on the computed duty cycle, and displaying the image using the color sequence. The generating comprises assigning a color cycle order to display time blocks in the color sequence, and assigning bitplane states for each display time block in the color sequence.

Abstract: System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.

Abstract: A system-on-chip (SOC) that includes a plurality of initiator components, and a target memory component coupled to the initiator components and having a target firewall, wherein the target firewall is configured to be programmed with a data structure which indicates, for at least one portion of the target memory component, access conditions for each initiator component.

Abstract: A pallet (501) supporting a half-etched leadframe with cantilever-type leads (403) without metallic supports during the step of attaching components (510) to the leads in order to assemble an electronic system. After assembly, the pallet is removed before the molding step that encapsulates (601a) the components on the leadframe and mechanically supports (601b) the cantilever leads. The pallet is machined from metal or inert plastic material, tolerates elevated temperatures during soldering, and is reusable for the next assembly batch.

Abstract: A method of performing wireless communications. The method receives at a receiving unit a sequence of data blocks from a transmitting unit. The method also identifies at the receiving unit a first number of invalid sequential data blocks in the sequence and a second number of valid sequential data blocks in the sequence. The method also communicates from the receiving unit a wireless message to the transmitting unit. The wireless message comprises a first field that specifies the first number and a second field that specifies the second number—the encoding of the first field is operable to specify a different maximum than an encoding of the second field.

Abstract: A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

Abstract: A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit.

Abstract: Single-ended sense amplifier circuit. An example of the sense amplifier circuit includes an inverter coupled to a bit line to read a bit cell. The sense amplifier circuit also includes a first circuit responsive to a control signal to charge the bit line for a predefined time. Further, the sense amplifier circuit includes a second circuit coupled to the bit line and responsive to a read 1 operation to retain voltage of the bit line above a first threshold to render the inverter to read 1 from the bit cell.

Abstract: One embodiment of the invention includes a system for writing data onto a magnetic disk. An output driver provides a first write current through a first output transistor in a first state and provides a second write current through a second output transistor in a second state. The first and second write currents can be provided to a disk write head to store opposing binary values, respectively. A bias current generator switches a first bias current between an intermediate voltage node in the second state and the first control node in the first state, and switches a second bias current between the intermediate voltage node in the first state and the second control node in the second state. The first and second bias currents can be provided to set a bias voltage at the first and second control nodes to bias the first and second output transistors, respectively.