Abstract: A semiconductor pressure sensor employing the piezoresistive effect of single crystal silicon resistors to measure the flexure of a semiconductor diaphragm. In the preferred embodiment, a Wheatstone bridge composed of a first pair of resistors disposed on the center of the diaphragm and a second pair of resistors disposed on the periphery of the diaphragm is employed. Due to the nature of the diaphragm flexure, the first and second pairs of resistors exhibit piezoresistivity in opposite directions enabling pressure measurement with greater sensitivity. The diaphragm is mounted on and supported by a silicon clamp ring. The diaphragm and the clamp ring together form a unitary semiconductor structure.

Abstract: A magnetic bubble memory chip structure on which a plurality of magnetic bubble storage loops are provided for containing information data as represented by bubbles and voids and including a dedicated area on the chip for containing redundancy data as represented by a chain of bubbles and voids arranged in a predetermined manner to identify good and defective information data storage loops. The redundancy data-containing dedicated area of the chip comprises a plurality of redundancy data-containing storage loops of equal number to the information data-containing storage loops so as to correspond thereto in a one-on-one relationship, with the number of individual bit positions included in each information data-containing storage loop being significantly greater than the number of bit positions included in each individual redundancy data-containing storage loop.

Abstract: A semiconductor memory device of the single-chip MOS/LSI one-transistor dynamic RAM cell array type stores both data and address in rows of the array and uses a high speed serial access shift register as its data input/output system. The serial shift register has a number of stages equal to the number of columns in the memory cell array, and data in the shift register is transferred into or out of the columns of the array when a comparator indicates that an address input matches the stored row address. The rows are sequentially activated by a commutator, so no row or column decoders are needed. The device may be made fault tolerant by use of an electrically programmable floating gate transistor connected to each row, and programming this transistor to blank input or output if the row includes bad cells. The fault tolerant feature is transparent to the computer system using the memory.

Abstract: An automated fluid flow measurement system employs two temperature sensitive silicon resistors having tracking temperature coefficients. The resistors have equal impurity concentration but different values of resistance. The first temperature sensitive resistor is employed to measure the temperature of a flowing fluid. The second temperature sensitive resistor is electrically heated to a temperature at a predetermined amount greater than the measured temperature of the fluid. Because the rate of heat transfer from the heated temperature sensitive resistor to the fluid depends upon the rate at which the fluid passes this temperature sensitive resistor, the power required in order to maintain the predetermined temperature difference in the second temperature sensitive resistor is a measure of the flow rate of the fluid.

Abstract: A signal processor has a single random access memory having a capacity equal to or greater than the total number of words in a processing interval. An address sequence mechanism is operatively connected to the memory for addressing the memory in a sequence for, after the first processing interval, reading out data for the first processing interval continuously in a preselected output order and overwriting data for the next processing interval continuously in a preselected input order in the locations of the data being read out. An address checker is connected to the address sequence mechanism for checking the addresses thereof for error and a controller is operatively connected to the address sequence mechanism, address checker, and memory for controlling their operation.

Abstract: A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.

Abstract: A negative, high energy radiation resist based on styrene-allyl methacrylate copolymers and substitutional modifications thereof, yielding a linear copolymer with highly sensitive allyl pendant groups together with a thermally stable, solvent resistant backbone. This resist exhibits improved e-beam sensitivity without the attendant problems of swelling during development and flow during heat processing.

Abstract: A metal oxide semiconductor device having at least one level of polycrystalline silicon interconnects and novel insulation layers for multilevel interconnects. In one embodiment a layer of arsenic doped glass replaces the conventional phosphorus doped glass insulation layer. In other embodiments a layer of arsenic doped glass upon an undoped layer of silicon dioxide provides the insulation layer. Slow diffusing source-drain impurities along with these insulation layers provide minimum lateral source-drain diffusion.

Abstract: A speech synthesis circuit implementable in an integrated circuit device, capable of converting frames of data into analog signals representative of human speech. The frames of data are comprised of digital representations of values of pitch, energy and certain filter coefficients, which are stored in non-volatile memory. The filter coefficients are utilized to control a linear predictive filter which is excited by voiced and unvoiced excitations stored in non-volatile memory. A control circuit coupling the excitation signals to the linear predictive filter allows the operator to select an external excitation signal rather than precalculated stored excitation signals. Thus, the synthesizer may be utilized in a vocoder application, wherein a residual excitation signal transmitted from an analysis circuit may be utilized as the excitation signal.

Abstract: A temperature compensated, phase tolerant sense amplifier for use in a magnetic bubble memory system in which current is applied to the detector resistors only during a bubble detect operation.

Abstract: Disclosed is a relay for high current equipment, such as, for example, an electric range. The relay provides the interface between the solid state electronics and the high wattage electric heating elements. The relay is comprised of a frame having a non-electrically conductive, flexible substrate, such as a plastic substrate supported at its ends with a shallow V cross section. The substrate has conductive heater elements formed thereon with heater terminals connected to said elements. The plastic substrate has a high coefficient of thermal expansion. A biasing member in contact with the apex of the plastic substrate transmits forces between the substrate and a switch assembly, either creep or snap acting. The upper switch arm preloads or couples a force between the biasing element and the plastic substrate causing a shallow V to be formed in the substrate. When current is applied to the heater terminals and heats the heater element, the substrate expands.

Abstract: An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

Abstract: An electrically programmable memory array of the floating gate type with a high coupling ratio is made by a DMOS process which allows the edges of the floating gates to be self-aligned with the edges of the control gates and produces improved characteristics in the form of higher gain and lower body effect. The source and drain regions are formed prior to applying the first level polysilicon by a process which leaves these regions covered with thick oxide, rather than using the polysilicon as a mask to define the gate areas. Double-diffused regions are formed on one or both sides of the channel, also beneath thick oxide, instead of using a P+ tank. The ratio of the capacitance between the floating gate and control gate to the total capacitance at the floating gate is increased and the degradation in the cell performance usually caused by the P+ tank is avoided.

Abstract: An electronic data processing system such as utilized in battery powered hand held calculators having a two mode clock control for control of power consumption. A power consumption controller enables generation of clock signals in an active cycling state for operating the data processing system in an active mode and enables generation of clock signals in a predefined steady state for operating the data processing system in a low power standby mode. In another embodiment of this invention, the power consumption controller generates a preset signal during the standby mode, this preset signal being applied to certain critical circuits of the data processing system to force each critical circuit output to a designer predefined output logic level during the standby mode. The designer predefined output logic level of each critical circuit is selected to prevent static power loads in the standby mode caused by node self discharge.

Abstract: A calculator having constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved.

Abstract: A transparent intelligent communication network characterized by the rythmic storage and forwarding of multi-user packets comprised of mini-packets of customer data, wherein interconnection bandwidth is dynamically expanded when normal currently received information is insufficient to occupy all available bandwidth, thereby reducing backlogs of stored information and increasing efficiency of use of channel capacity.

Abstract: A thermostat device has control means movable between control positions on a base when a thermostat metal element moves with snap action in response to temperature changes. Angle-shaped mounting brackets of a relatively high strength metal material have respective legs fitted against a boss on the base periphery and a cup-shaped cap of a relatively more formable and more thermally conductive metal is fitted over the thermostat metal element on the base to enclose the noted legs of the brackets.

Abstract: A transparent intelligent communication network having both terrestrial and satellite links between nodes and providing improved channel utilization by including a system of reservations through successive links for the incoming data.

Abstract: A remotely controlled circuit breaker system incorporates a generally conventional circuit breaker having latch means which are moveable in a first direction for moving an operating member so that it is latched in closed circuit position, the operating member being adapted to be independently moveable in the same first direction for unlatching the member to permit the member to return to its open circuit position. A momentarily operable solenoid has a pawl pivotally mounted on the solenoid plunger. Spring means resiliently hold the pawl against a stop in a selected location relative to the latch means so that when the solenoid is momentarily actuated while the operating member is in open circuit position, the pawl engages the latch means and moves the operating member to its latched closed circuit position.

Abstract: A data processing system which contains a read-only memory circuit, an arithmetic circuit, and a control circuit on a single semiconductor chip including a clock generating circuit for supplying system clocks to all of the circuits on the chip and the clock generating circuit is structured such that on the input of an external halt signal, the clock circuits will cease supplying system clocks during a period that provides for information contained within the system on the semiconductor chip.