Abstract: An MOS memory cell of the static type employs a pair of cross-coupled driver transistors forming a bistable circuit, with load resistors replaced by a pair of series coupling transistors connecting storage nodes to complementary precharged data lines. A two phase clock turns on the coupling transistors in sequence, for refresh, so an intermediate node is charged during a first phase and discharged into the storage nodes during the second phase. Both transistors are turned on at the same time for read or write operations.

Abstract: A heat responsive electrical switch comprises a small, open ended, generally cylindrical housing in which are mounted two spaced plate members extending in parallel directions from a bottom wall into a switch cavity. The first plate member mounts at its distal free end a relatively inflexible movable contact arm which is adapted to move into and out of engagement with a stationary contact mounted on the second plate member. A relatively low spring rate spring is connected between the movable contact arm toward the stationary contact with a selected contact force created by displacing a portion of the spring with a reaction force. The open end of the housing is formed with a plurality of raised plateaus. A thermally conductive cup is received over the open end interfitting with the plateaus. A thermally responsive snap-acting disc and a flexible motion transfer sheet of resinous material can be captured by the cup at the open end of the housing.

Abstract: Control signals are transmitted through a.c. mains supply lines to control operation of electrical equipment powered from the supply lines. A near short-circuit condition is introduced across the a.c. mains supply lines, for example, by firing a thyristor connected in series with a fuse across the supply lines, for the final portion of positive half cycles of the mains supply voltage, thus holding the voltage to a near zero value for this length of time. A receiver coupled to the mains supply lines includes a zero crossing detector circuit which responds to the near zero voltage conditions across the supply lines to perform a particular control operation on an associated appliance connected to the receiver. Different control operations may be effected by defining the control signals over a group of half cycles of the a.c.

Abstract: Disclosed is an electronic calculator having a data entry unit for inputting numeric data, expressions such as parentheses and hierarchal mathematical commands, an arithmetic unit for performing arithmetic operations on the numeric data, a memory for storing the numeric data and associated hierarchal mathematical commands inputted via the data entry unit and logic circuitry for enabling the arithmetic unit to perform arithmetic operations on numeric data inputted via the data entry unit within a pair of parentheses, the logic circuitry enabling the arithmetic unit to perform a higher order hierarchal mathematical command before a lower order hierarchal command eventhough the higher order command is received after the lower order hierarchal mathematical command.

Abstract: A semiconductor memory device of the single-chip MOS/LSI integrated circuit type has both serial access and random access arrays on the same chip. When the device is addressed, if the address is in the random access portion then data input or output is the same as in dynamic RAM operation, but if the address is in the serial arrays then access is different. For a read operation a row containing the addressed data is transfered serially from the serial access portion to a shift register coupled to the random access array, then this row of data is transfered into the columns of the array and output is accomplished in the usual manner. The random access or serial access arrays may be loaded serially.

Abstract: A switching power supply has a power switching transistor furnishing a series of shaped pulses to output means for providing an output voltage, has control means including a voltage controlled oscillator responsive to the output voltage for providing control pulses whose frequency is representative of the output voltage level, and has saturable transformer means coupling the control pulses to the switching transistor for driving the transistor to regulate the output voltage within a selected range. First winding means on the saturable transformer drive the transformer to saturation with each control pulse and other winding means forward bias the switching transistor to conduct while the transformer is being driven to saturation and thereafter reverse bias the transistor to rapidly turn it off as the transformer recovers from saturation. The power supply includes means for varying transistor switching frequency and pulse width for regulating output voltage.

Abstract: A chart recorder has a fixed thermal printhead for recording traces and annotations thereto representative of monitored parameters. A microcomputer, including timing, memory and control circuits controls the operation of the recorder which is enabled to print one or more traces simultaneously. The microcomputer control enables the printing of limit parameters, grids and times along with the traces. Further, the microcomputer provides for linearization of nonlinear parameters to be measured such as thermocouple temperature measurements and the like.

Abstract: An annunciator is disclosed which has an improved charging circuit for storing the energy of a ring signal received via an improved Schottky diode bridge rectifier, and an oscillator-driven variable divider which actuates an audible output device when the stored charge exceeds a threshold level.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: A nonlinear transmission line terminator terminates a transmission line having an input from any one of a plurality of logic types. Emitter coupled logic (ECL), transistor logic (TTL), Schottky transistor logic (STTL), low power Schottky transistor transistor logic (LSTTL), complementary MOS (CMOS) and the like are accommodated by impressing the voltage representing a "0" of the logic circuitry being accommodated on one reference terminal and the corresponding "1" voltage on another reference terminal. The terminator presents a very high impedance when the input signal from the transmission line is of an amplitude falling within the "0" and "1" voltage range. When the input signal falls outside the voltage range, the impedance of the terminator matches that of the transmission line to reduce line reflections by providing a path for current to flow from the transmission line to the appropriate one of the "1" or "0" reference terminals.

Abstract: Apparatus for rounding of a character produced as a character segment matrix pattern for display on a raster scanned display in which a read-only memory storing the character segment matrix patterns for the characters to be displayed is arranged to produce the entire matrix pattern for a selected character in parallel at any one time. A parallel gating means selects from the matrix pattern a selected row of the matrix and also the immediately preceding row or the immediately following row depending upon which is required at the time for character rounding. The bits of the selected row are applied in parallel to a first shifting register and the bits of both rows produced by the gating means are applied in parallel to a character rounding logic circuit which is arranged to detect the presence of diagonal lines in the character and produce the appropriate rounding elements.

Abstract: A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh address generator circuitry including an address counter or commutator and a multiplexer to insert the refresh address when a command is received or internally generated indicating a refresh cycle. If a refresh command is not being executed, the device is accessed in the usual manner if a memory address is received.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. In a programming mode of operation, the application of high voltages to the row and column lines is controlled to prevent programming voltage from reaching a selected column until after all transistors in a row are turned on by programming voltage on a row line. This prevents unwanted programming conditions.

Abstract: A system using a digital filter for generating complex waveforms, such as human speech. The filter has a multiplier, an adder coupled to the output of the multiplier and various delay circuits coupled to the output of the adder. A latch memory is coupled to the output of one of the delay circuits. Switching circuits are provided for the output of the delay and the latch memory to inputs of the multiplier and the adder to selected times. Coefficients of the filter are preferably stored in a memory coupled to another input of the multiplier. The excitation signal is coupled to the adder in one embodiment and to the multiplier in another embodiment.

Abstract: A compact, low cost, pressure responsive electrical switch of improved reliability has simple and easily assembled contacts movable on a base between open and closed circuit positions. A dished metal disc is operably connected with a diaphragm to move with snap action between original and inverted dished configurations for moving the contacts sharply between such circuit positions when selected pressures are applied to the diaphragm.

Abstract: A CMOS switching circuit is disclosed which switches between first and second input signals, which are preferably phase and frequency related, in response to changes in the logical condition of a control signal.

Abstract: Method and apparatus for removing a photoresist layer from a substrate surface of different material, such as a semiconductor slice, in the fabrication of an electronic structure, involving exposure of the photoresist layer to an ozone-containing gaseous atmosphere in a reaction zone of a reactor. The ozone is present as an active reagent in the gaseous atmosphere to which the layer of photoresist material is exposed in an amount sufficient to react with all of the photoresist material in the layer thereof, with the photoresist material being removed from the underlying substrate surface in response to its exposure to the ozone. The photoresist material being treated by the ozone for stripping thereof may be either a negative or positive photoresist.

Abstract: A monitor for optimizing the ultrasonic bonding of materials by analyzing the impedance of an ultrasonic transducer used to effect the bond. The electrical impedance of the transducer, which is proportional to its mechanical impedance, is determined by applying an ultrasonic voltage thereto and monitoring the resultant change in current amplitude. A pair of differentiators produces a second derivative signal of the impedance with respect to time, with a negative-going zero crossing of this signal corresponding to completion of the bond. Loss of wire, mechanical malfunctions and improper bonds are also detected by the monitor, to form a real time quality control system.

Abstract: A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the calculator. The calculator also includes a program counter, an instruction register, control decoders, data storage array, a decimal arithmetic logic unit, an output decoder, and a digit scanner which scans both the keyboard and display outputs. Aside from providing basic desk top calculator functions, the read only memory may be programmed so that the system provides metering functions, arithmetic teaching functions, control functions, etc., and to accommodate these different uses the output decoder is mask-programmable. A preferred embodiment of the invention is capable of being fabricated as a monolithic integrated semiconductor system utilizing contemporary metal-insulator-semiconductor techniques.

Abstract: An MOS read only memory or ROM is formed by a process compatible with standard P or N channel metal gate manufacturing methods. The ROM is programmed at a late stage of the process after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon with an overlying patterned metal layer and output and ground lines are defined by elongated heavily doped regions. Thin gate oxide is formed for every gate position, rather than for only the selected gates as in the prior standard programming method. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by ion implanting through the polysilicon gates where metal has been removed, using photoresist as a mask.