Abstract: An electrical system includes a power supply and an electrical circuit coupled to the power supply and including an operational amplifier. The operational amplifier includes an input stage and a pre-driver stage coupled to the input stage, wherein the pre-driver stage includes a first input terminal, a second input terminal, and a voltage supply terminal. The operational amplifier also includes an output stage with bipolar transistors coupled to the pre-driver stage. The pre-driver stage is configured to: detect a voltage differential across the first and second input terminals of the pre-driver stage; and provide an adjustable bias current based on the voltage differential.

Abstract: A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.

Abstract: In a described example, a bipolar junction transistor includes a substrate. An emitter region, a base region, and a collector region are each formed in the substrate. A gate-type structure is formed on the substrate between the base region and the emitter region. A contact is coupled to the gate-type structure, and the contact is adapted to be coupled to a source of DC voltage.

Abstract: A receiver circuit includes an ADC, a processing channel, and an interference detection path. The processing channel is configured to process data samples provided by the ADC, and includes a notch filter. The interference detection path is configured to detect interference in the data samples, and includes a slicer, a slicer error circuit, and an interference detection circuit. The slicer is configured to slice input of the notch filter. The slicer error circuit is configured to compute an error of the slicer. The interference detection circuit configured to detect an interference signal in the error of the slicer, and set the notch filter to attenuate the interference signal.

Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.

Abstract: A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

Abstract: A driver assistance system includes a first camera, a second camera, a first serial interface circuit, a second serial interface circuit, and a hub interface circuit. The first serial interface circuit is coupled to the first camera. The second serial interface circuit is coupled to the second camera. The hub interface circuit is coupled to the first serial interface circuit and the second serial interface circuit. The hub interface circuit is configured to receive transmissions from the first serial interface circuit and the second serial interface circuit, and to transmit control information to the first serial interface circuit and the second serial interface circuit. The hub interface is also configured to encode a clock signal in the control information.

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Abstract: A circuit includes a first transistor, a second transistor, and a sense transistor. The first current terminals of the first and second transistors are coupled together at a power supply node. The control terminals of the second and third transistors are coupled together. The second current terminals of the first, second, and third transistors are coupled together. The sense resistor is coupled between the first current terminals of the first and second transistors and the first current terminal of the third transistor. The first and second transistors are configured such that during a first mode of operation, current to a load flows through the first and second transistors, and during a second mode of operation, current to a load is discontinued through the first transistor yet flows through the second transistor.

Abstract: One example includes a receiver system. The receiver system includes an analog-to-digital converter (ADC) configured to convert an analog input signal into a digital output signal at a sampling frequency. The receiver system also includes a spur correction system configured to receive the digital output signal and to estimate spurs associated with the digital output signal and to selectively correct a subset of the spurs associated with a set of frequencies that are based on the sampling frequency.

Abstract: An electronic device includes a multilevel package substrate, a die, a lid, and a package structure that encloses the die, a portion of the lid, and a portion of the multilevel package substrate, where the package structure fills a gap between a side of another portion of the lid and a side of the die. A method includes attaching a die to a multilevel package substrate with a first side of the die facing the multilevel package substrate and a second side facing away from the multilevel package substrate; positioning a lid on the multilevel package substrate with a first portion of the lid spaced apart from the second side of the die; and forming a package structure that encloses the die and a portion of the multilevel package substrate and fills a gap between the first portion of the lid and the second side of the die.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for allocation in a victim cache system. An example apparatus includes a first cache storage, a second cache storage, a cache controller coupled to the first cache storage and the second cache storage and operable to receive a memory operation that specifies an address, determine, based on the address, that the memory operation evicts a first set of data from the first cache storage, determine that the first set of data is unmodified relative to an extended memory, and cause the first set of data to be stored in the second cache storage.

Abstract: A method includes executing software code comprising a plurality of execute packets; responsive to an execute packet of the software code being executed by a data processor core, advancing a value of a test counter register; and responsive to the value of the test counter register being equal to a terminal value, triggering an event to be handled by the software code.

Abstract: Some aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes an integrator coupled between a first node and a second node and a filter coupled between the second node and a third node. The circuit further includes a buffer coupled between the third node and a fourth node and a first switch coupled between the fourth node and a fifth node. The circuit further includes a first capacitor coupled between the fifth node and a ground node, a first resistor comprising a first terminal coupled to the fifth node and a second terminal, a second switch coupled between the second terminal of the first resistor and the ground node.

Abstract: In the described examples, a driver includes a signal controller that provides a gate control signal to a gate buffer coupled to a gate of a transistor and a field plate control signal to a field plate buffer coupled to a field plate of the transistor. The signal controller provides a rising edge on the field plate control signal causing the field plate buffer to provide a bias voltage on the field plate of the transistor a predetermined amount of time after providing a rising edge on the gate control signal that causes the gate buffer to provide a turn-on voltage on the gate of the transistor that causes the transistor to transition from a cutoff region to a saturation region and to a linear region.

Abstract: A FMCW radar receiver includes a LO providing a chirped LO signal, an in-phase (I) channel for outputting I-data and a quadrature (Q) channel for outputting Q-data. A dynamic correction parameter generator generates IQ phase correction values (P[n]s) and IQ gain correction values (G[n]s) based on a frequency slope rate of the chirped LO signal for generating during intervals of chirps including a first sequence of P[n]s and G[n]s during a first chirp and a second sequence of P[n]s and G[n]s during a second chirp. An IQ mismatch (IQMM) correction circuit has a first IQMM input coupled to receive the I-data and a second IQMM input receiving the Q-data, and the P[n]s and G[n]s. During the first chirp the IQMM correction circuit provides first Q?-data and first I?-data and during the second chirp the IQMM correction circuit provides at least second Q?-data and second I?-data.

Abstract: A method for determining intra-prediction modes for prediction units (PUs) of a largest coding unit (LCU) is provided that includes determining an intra-prediction mode for each child PU of a PU, and selecting an intra-prediction mode for the PU based on the intra-prediction modes determined for the child PUs.

Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.

Abstract: A comparator includes an input stage having a differential input and an output, wherein the voltage at the output is in response to the voltage at the input. The comparator further includes a current limiter for limiting the current flow through the input stage, wherein the current flow through the input stage is in response to the voltage at the input.