Abstract: The disclosure provides a preparation method of GaN field effect transistor based on diamond substrate, and relates to the technical field of semiconductor manufacturing. The method includes the following steps: preparing a GaN heterojunction layer on the front-side of a SiC substrate; thinning the SiC substrate; etching the SiC substrate; growing a diamond layer; removing a sacrificial layer and the diamond layer on the sacrificial layer; preparing a source electrode, a drain electrode and a gate electrode on the front surface of the GaN heterojunction layer; etching the SiC substrate and the GaN heterojunction layer to form a source through hole communicated with the source electrode; and removing the through hole mask layer, and preparing back grounding metal to complete the preparation of the diamond substrate GaN transistor device.

Abstract: Disclosed is an apparatus for preparing a large-size single crystal, which relates to the field of semiconductor material preparation, and more particularly, to an apparatus for preparing a large-size single crystal from a plurality of small-size single crystals by connecting them in solid states. The apparatus includes a hydrocooling furnace, a solid connection chamber hermetically disposed in the hydrocooling furnace, and combined fixtures provided in the solid connection chamber, wherein a plurality of crystal pieces are fixed by the combined fixtures, a top column or a stress block is used for pressing the crystal piece through the combined fixtures, a heating wire surrounding the solid connection chamber is provided in the hydrocooling furnace, a vacuum tube is communicated with the solid connection chamber, and a thermocouple is disposed close to the combined fixtures.

Abstract: A three-dimensional displacement compensation method is provided. The method includes an obtaining step, a transforming step, a first determining step, a first calculating step and a compensating step. The obtaining step includes obtaining a current image of a measured element captured by a microscopic thermoreflectance thermography device. The transforming step includes two sub-steps. One sub-step uses Fourier transform to calculate a reference image to obtain a first result, and the other sub-step uses Fourier transform to calculate the current image to obtain a second result. The first determining step includes determining a peak point coordinate and a fitting diameter of a point spread function of an optical system of the device. The first calculating step includes calculating a three-dimensional displacement of the position to be compensated relative to the reference position. The compensating step compensates the position to be compensated.

Abstract: The disclosure relates to the technical field of semiconductors, and discloses a method for manufacturing a resonator. The method includes: a substrate is pretreated to change a preset reaction rate of a preset region part of the substrate, so that the preset reaction rate of the preset region part is higher than that of a region outside the preset region part; a preset reaction is performed to the substrate to form a sacrificial material part including an upper half part above an upper surface of the substrate and a lower half part below a lower surface of the substrate; a multilayer structure is formed on the sacrificial material part, and includes a lower electrode layer, a piezoelectric layer and an upper electrode layer from bottom to top; and the sacrificial material part is removed.

Abstract: A method includes: constructing an on-wafer calibration piece model set that includes one or more on-wafer calibration piece models, where each of the one or more on-wafer calibration piece models has a corresponding on-wafer calibration piece; selecting an on-wafer calibration piece model from the on-wafer calibration piece model set; measuring the on-wafer calibration piece utilizing an on-wafer S parameter measurement system that is calibrated using a multi-thread TRL calibration method in a Terahertz frequency band, to obtain an S parameter of the on-wafer calibration piece; and calculating a plurality of different parameters that represent crosstalk of calibration pieces in the on-wafer calibration piece model, according to an admittance calculated according to the S parameter and an admittance formula corresponding to the on-wafer calibration piece model.

Abstract: A multi-level converter control method is provided that includes: acquiring an inductive current of an LC filter in a driving pulse period; determining a to-be-adjusted first switch tube and a first duty ratio adjustment amount of the to-be-adjusted first switch tube based on a slope of a rising period of the inductive current, and adjusting a duty ratio of the to-be-adjusted first switch tube based on the first duty ratio adjustment amount; and determining a to-be-adjusted second switch tube and a second duty ratio adjustment amount of the to-be-adjusted second switch tube based on a slope of a falling period of the inductive current, and adjusting a duty ratio of the to-be-adjusted second switch tube based on the second duty ratio adjustment amount.

Abstract: The present application provides a trisection power divider with isolation and a microwave transmission system, where the divider includes a first hybrid ring coupler with a distribution ratio of 1:2 and a second hybrid ring coupler with a distribution ratio of 1:1; a first port of the first hybrid ring coupler is a signal input port; a second port of the first hybrid ring coupler is connected with a first port of the second hybrid ring coupler; a second port of the second hybrid ring coupler, a third port of the second hybrid ring coupler and a third port of the first hybrid ring coupler are three signal output ports of the divider; and the second port of the first hybrid ring coupler is a port with high power.

Abstract: The disclosure provides a resonator and a filter. The resonator includes: a substrate; and a multilayer structure formed on the substrate. The multilayer structure successively includes a lower electrode layer, a piezoelectric layer and an upper electrode layer from bottom to top. A cavity is formed between the substrate and the multilayer structure, and the cavity includes a lower half cavity below an upper surface of the substrate and an upper half cavity beyond the upper surface of the substrate and protruding toward the multilayer structure. A resonator with novel structure and good performance is formed by providing the cavity with the lower half cavity below the upper surface of the substrate and the upper half cavity above the upper surface of the substrate.

Abstract: A packaging structure includes: a substrate provided with a through-cavity penetrating up and down, and a metal heat sink on a front surface of the substrate; a bonding chip mounting area and a first passive element mounting area on the front surface, and a flip chip mounting area, a second passive element mounting area and a pin lead mounting area are provided on a back surface of the substrate; a first sealing ring located at the periphery of the bonding chip mounting area and the first passive element mounting area; a first cover plate packaged on the first sealing ring; a second sealing ring located at the periphery of the flip chip mounting area and the second passive element mounting area with the pin lead mounting area being located at the periphery of the second sealing ring; and a second cover plate packaged on the second sealing ring.

Abstract: The invention discloses a method for preparing an indium phosphide crystal by using an indium-phosphorus mixture, belongs to the technical field of semiconductors, and comprises the steps of preparing an indium-phosphorus mixed ball, charging, maintaining the high furnace pressure and the low temperature of the indium-phosphorus mixed ball, melting a covering agent, feeding, synthesizing and crystal growing, which is synthesized by directly melting the proportioned indium-phosphorus mixed ball. Indium powder and phosphorus powder are uniformly mixed and pressed into spherical indium-phosphorus mixed particles, then the mixture of the indium-phosphorus mixed balls and the boron oxide powder is fed into a melt with a boron oxide covering agent, and crystal growth in situ is performed after synthesis.

Abstract: A gallium oxide Schottky barrier diode with negative beveled angle terminal and a production method thereof are provided. The production method includes four steps. In the first step, a photoresist layer with a preset pattern is formed on a gallium oxide epitaxial layer, where the gallium oxide epitaxial layer is formed on an upper surface of a gallium oxide substrate. In the second step, first electrode layer is formed on the gallium oxide epitaxial layer. In the third step, the gallium oxide substrate is rotated and the gallium oxide epitaxial layer is etched. In the fourth step, a second electrode layer is formed on the lower surface of the gallium oxide substrate.

Abstract: The present application provides two-port on-wafer calibration piece circuit models and a method for determining parameters. The method includes: measuring a single-port on-wafer calibration piece circuit model corresponding to a first frequency band to obtain a first S parameter; calculating, according to the first S parameter, an intrinsic capacitance value of a two-port on-wafer calibration piece circuit model corresponding to the single-port on-wafer calibration piece circuit model; measuring the two-port on-wafer calibration piece circuit model corresponding to the terahertz frequency band to obtain a second S parameter; and calculating a parasitic capacitance value and a parasitic resistance value of the two-port on-wafer calibration piece circuit model according to the second S parameter and the intrinsic capacitance value.

Abstract: A semiconductor phosphide injection synthesis system and a control method are provided, which belong to the technical field of preparation of semiconductor phosphides. The semiconductor phosphide injection synthesis system includes a furnace body, a shielding carrier box arranged above the furnace body by virtue of a lifting mechanism, a phosphorus source carrier arranged in the shielding carrier box, an injection pipe arranged below the phosphorus source carrier, and a crucible arranged at an inner bottom of the furnace body in a matched manner.

Abstract: The disclosure provides a normally-off gallium oxide field-effect transistor structure and a preparation method therefor, and relates to the technical field of semiconductor device. The normally-off gallium oxide field-effect transistor structure comprises a substrate layer and an n-type doped gallium oxide channel layer from bottom to top. The n-type doped gallium oxide channel layer is provided with a source, a drain, and a gate. The gate is located between the source and the drain. A no-electron channel region is provided in the n-type doped gallium oxide channel layer located below the gate.

Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Abstract: A calibration method includes: acquiring eight error models obtained after a preliminary calibration of a Terahertz frequency band system; based on the eight error models, determining a first mathematical model according to a first S parameter related to a first calibration piece, the first mathematical model comprising parallel crosstalk terms between probes, and determining a second mathematical model according to a second S parameter related to a second calibration piece, the second mathematical model comprising series crosstalk terms between the probes; determining a third mathematical model according to a third S parameter related to a measured piece; and solving and obtaining a Z parameter of the measured piece based on the first mathematical model, the second mathematical model and the third mathematical model, and acquiring an S parameter of the measured piece according to the Z parameter of the measured piece.

Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.

Abstract: A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.

Abstract: The disclosure provides a calibration method, a system and a device of an on-wafer S parameter of a vector network analyzer. The method comprises the steps of: acquiring a first parameter of a first crosstalk calibration piece measured by the vector network analyzer; obtaining a main crosstalk error term based on the first parameter of the first crosstalk calibration piece and a calibration parameter of the first crosstalk calibration piece; acquiring a second parameter of a second crosstalk calibration piece measured by the vector network analyzer based on the main crosstalk error term; and obtaining a secondary crosstalk error term based on the second parameter of the second crosstalk calibration piece and a calibration parameter of the second crosstalk calibration piece, wherein the main crosstalk error term and the secondary crosstalk error term are used for calibrating the vector network analyzer.

Abstract: The invention provides a growth method for preparing high-yield crystals, belongs to the technical field of single crystal growth. Auxiliary crucibles are arranged on a crucible according to different crystal types and according to the crystal orientation of crystal growth in the main crucible, the relationship between the crystal growth direction and twin crystal orientation. By controlling the angle between the auxiliary crucibles and the main crucible, the relative position between the auxiliary crucibles each other, the auxiliary crucibles realize correction on the crystal orientation of twins generated in the main crucible crystal growth process.