Abstract: An unbalanced terahertz frequency doubler circuit with power handling capacity is provided, and the circuit includes a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Abstract: The present application discloses an unbalanced terahertz frequency doubler circuit with power handling capacity including a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Abstract: The present invention discloses a method for carrying out phosphide in-situ injection synthesis by carrier gas, relating to a synthetic method of semiconductor crystal: step A, shielding inert gas is introduced into a furnace body through a carrier gas intake conduit; step B, a crucible is heated in the furnace body to melt a pre-synthesized raw material in the crucible; step C, the heated shielding inert gas is introduced into the furnace body through the carrier gas intake conduit; step D, a phosphorus source furnace loaded with red phosphorus is moved downwards until an injection conduit of the phosphorus source furnace is submerged in the melt; step E, the red phosphorus is heated by the phosphorus source furnace to produce phosphorus gas, and the phosphorus gas is mixed with the shielding inert gas and then injected into the melt through the injection conduit, and the phosphorus gas reacts with the melt to produce phosphide; and step F, each device is turned off after the synthesis is finished.

Abstract: The invention provides a device and method for continuous VGF crystal growth through rotation after horizontal injection synthesis, and belongs to the technical field of semiconductor crystal synthesis and growth.

Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: The application discloses a parallel seam welding leadless ceramic package, including a ceramic, a sealing ring and a metal cover plate; a back surface of the ceramic is provided with a back grounding metal pattern, and the back grounding metal pattern is provided with several outwardly protruding grounding terminals, a RF signal transmission pad is disposed between every two adjacent grounding terminals, the front grounding metal pattern and the back grounding metal pattern are interconnected by the internal and/or external metallized interconnection holes, the front grounding line and the back grounding metal pattern is interconnected by the internal or external metallized interconnection holes, and the RF signal transmission lines are interconnected to the RF signal transmission pad by a separated external and/or external metallized interconnection hole.

Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.

Abstract: Disclosed is a refined white ceramic material, which belongs to the field of ceramic materials for component packaging, and comprises the following raw materials by weight in percentage: aluminum oxide 87-93, magnesium oxide 0.8-5, silicon dioxide 1-6, calcium oxide 0.6-4, titanium dioxide 0.01-0.5, and zirconium dioxide 0.5-3. The method for preparing same comprises: (1) washing aluminum oxide grinding balls and a ball-milling tank, and drying for later use; (2) weighing a solvent NP-10 of 0.5-4 by weight in percentage, and adding the solvent into the ball-milling tank; (3) weighing raw materials, adding the raw materials into the ball-milling tank, and performing ball milling for 72±0.5 h. By means of the refined white ceramic material of the present invention, the obtained ceramic grains have even sizes, small surface roughness, and high fracture resistance performance of ceramic body.

Abstract: Disclosed is a refined white ceramic material, which belongs to the field of ceramic materials for component packaging, and comprises the following raw materials by weight in percentage: aluminum oxide 87-93, magnesium oxide 0.8-5, silicon dioxide 1-6, calcium oxide 0.6-4, titanium dioxide 0.01-0.5, and zirconium dioxide 0.5-3. The method for preparing same comprises: (1) washing aluminum oxide grinding balls and a ball-milling tank, and drying for later use; (2) weighing a solvent NP-10 of 0.5-4 by weight in percentage, and adding the solvent into the ball-milling tank; (3) weighing raw materials, adding the raw materials into the ball-milling tank, and performing ball milling for 72±0.5 h. By means of the refined white ceramic material of the present invention, the obtained ceramic grains have even sizes, small surface roughness, and high fracture resistance performance of ceramic body.