Abstract: A system for inspecting an aircraft at a first location, includes an imaging device configured to acquire one or more images of one of or more surfaces of the aircraft at the first location. A control unit is in communication with the imaging device. The control unit is configured to receive the one or more images. A user interface is in communication with the control unit. The user interface is at a second location that differs from the first location. The user interface includes a display. The control unit is configured to show the one or more images on the display. As such, the inspection is performed at the first location, such as by an individual using the display.

Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

Abstract: Blending of polyvinylchloride (PVC) and other rigid polymers may be facilitated using lubricant compositions comprising linear alpha olefins (LAOs) or compounds derived from LAOs. PVC blending methods may comprise: combining PVC and a lubricant composition to form a mixture, and blending the mixture to form a lubricated PVC blend, in which the mixture contains an effective amount of the lubricant composition to provide a fusion temperature for the lubricated PVC blend of about 190° C. or below as determined by torque rheometry at 65 rpm. The lubricant composition may comprise one or more C18+ linear alpha olefins (LAOs) having a kinematic viscosity of about 4 cSt or less at 135° C., or one or more LAO dimers formed from the one or more C18+ LAOs, the one or more LAO dimers having an internal olefin and a kinematic viscosity of about 6 cSt or less at 135° C., or reduced LAO dimers.

Abstract: A semiconductor device includes a first gate, a second gate disposed over the first gate, a first contact, a second contact, a third contact disposed between the first gate and the second gate, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer is disposed between the first gate and the third contact. The first semiconductor layer includes a first channel region, a first source region, and a first drain region, and the first channel region laterally extends between the first drain region and the first contact. The second semiconductor layer is disposed between the second gate and the third contact. The second semiconductor layer includes a second channel region, a second source region, and a second drain region, and the second channel region laterally extends between the second drain region and the second contact.

Abstract: Provided is a polishing tool and a methods for polishing a wafer or manufacturing a semiconductor device. A method for polishing a wafer includes contacting a surface of the wafer to a polishing pad at an interface; rotating the wafer and/or the pad; and delivering a series of selected treatment agents to the interface and removing waste from the interface through channels extending through the pad, while controlling a rate of delivering the selected polishing agents and removing the waste streams through the channels formed in the pad to optimize polishing of the wafer.

Abstract: Disclosed is a compound of Formula (Ib): The compound of Formula (Ib) is useful for positron emission tomography (PET) imaging of Bruton's Tyrosine Kinase (BTK) in mammals. Also disclosed are methods of using the compound as a labeling and diagnostic imaging agent of Bruton's Tyrosine Kinase (BTK), and methods of preparing Compound (Ib).

Abstract: An optical modulator includes a waveguide. The waveguide includes a first optical coupling region, a first electrical coupling region, and a first plurality of regions. The first optical coupling region is doped with first dopants. The first electrical coupling region is doped with the first dopants. The first plurality of regions are doped with the first dopants and are sandwiched between the first optical coupling region and the first electrical coupling region. The first plurality of regions have respective decreasing doping concentrations as distances of the first plurality of regions increase from the first electrical coupling region. The first plurality of regions have respective decreasing heights as the distances of the first plurality of regions increase from the first electrical coupling region. A maximum doping concentration of the first plurality of regions is smaller than a doping concentration of the first electrical coupling region.

Abstract: The present disclosure relates to a message transmission method and related devices. The method is performed by an application function (AF), and includes: transmitting a first quality of service (QoS) request message to a policy control function (PCF), the first QoS request message including first connection identity (ID) information and a first QoS parameter; and the first QoS request message being configured for instructing the PCF to transmit, according to the first QoS request message, a first policy control and charging (PCC) rule to a first session management function (SMF), the first PCC rule including the first connection ID information and the first QoS parameter. The embodiments of this application can optimize network transmission, and reduce the quantity of times of interaction between the AF and the network.

Abstract: In an example implementation according to aspects of the present disclosure, a XR system comprises an HMD which includes an HMD display, a user input device, and a processor operatively coupled with a computer readable storage medium and instructions stored on the computer readable storage medium that, when executed by the processor, direct the processor to display, by the HMD display, an XR keyboard to a user of the HMD, wherein the XR keyboard comprises keys lined along the perimeter of the XR keyboard; display, by the HMD display, at least one projection line indicating a selection direction by the user; capture, by the user input device, a movement of the at least one projection line across a key on the perimeter of the XR keyboard displayed on the HMD display; and identify a key selected based on the captured movement across the key.

Abstract: A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Abstract: A method for estimating relative humidity inside an electrical machine includes determining a measured rate of change (ROC) of temperature inside an electrical machine. A ratio of the measured ROC to a reference ROC is calculated, where the ratio is equal to an average specific heat of the electrical machine. The average specific heat of the electrical machine and an air temperature value are then compared to known specific heat values of dry air and water corresponding to a known relative humidity values for a range of air temperatures. A relative humidity value inside the electrical machine is estimated based on the comparison.

Abstract: A manufacturing method of a package-on-package structure includes forming a first package structure and staking a second package structure over the first package structure. The first package structure is formed by at least the following steps. A first redistribution structure is provided. Conductive structures are formed on the first redistribution structure. A die is placed between the conductive structures. The die and the conductive structures are encapsulated by an encapsulant. The encapsulant is planarized such that an entirety of a top surface of the encapsulant is coplanar with an entirety of top surfaces of the conductive structures. A second redistribution structure is formed on the encapsulant. The second redistribution structure includes a conductive pattern layer that is in physical contact with the top surfaces of the encapsulant and the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height.

Abstract: An apparatus including an integrated reference electrode and a fluid dispenser is described. The reference electrode includes a body and a tip. The fluid dispenser at least partially surrounds the tip of the reference electrode and includes an inlet, a chamber, and an outlet. The fluid dispenser is configured to receive a fluid sample from the inlet to the chamber and form a droplet of the fluid sample through the outlet so that the droplet is in fluidic contact with the tip of the reference electrode and associated with a known potential determined by the reference electrode.

Abstract: In some aspects of the present disclosure, a bandgap reference circuit includes a first current mirror and a first resistor coupled to the first current mirror to provide a proportional to absolute temperature (PTAT) voltage. The circuit includes a second current mirror and a bipolar junction transistor (BJT) device coupled to the second current mirror to provide a complementary to the absolute temperature (CTAT) voltage. The circuit includes an output node to provide a bandgap voltage that is a weighted sum of the PTAT voltage and the CTAT voltage. The circuit includes a second resistor coupled between the output node and a first node, wherein the first node is coupled between the first resistor and the first current mirror. The circuit includes a third resistor coupled between the output node and a second node, wherein the second node is coupled between the BJT device and the second current mirror.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

Abstract: A semiconductor device includes a first three-dimensional semiconductor structure of a first conductivity type protruding from a surface of a semiconductor substrate, a second three-dimensional semiconductor structure of a second conductivity type also protruding from the surface of the semiconductor substrate, and a first transistor. The first transistor includes a first source/drain structure formed in the first three-dimensional semiconductor structure, a second source/drain structure formed in the second three-dimensional semiconductor structure, and a first gate structure straddling a first portion of the first three-dimensional semiconductor structure and a first portion of the second three-dimensional semiconductor structure.

Abstract: A three-dimensional memory device and a manufacturing method thereof are provided. The three-dimensional memory device includes first and second stacking structures, isolation pillars, gate dielectric layers, channel layers and conductive pillars. The stacking structures are laterally spaced apart from each other. The stacking structures respectively comprises alternately stacked insulating layers and conductive layers. The isolation pillars laterally extend between the stacking structures. The isolation pillars further protrude into the stacking structures, and a space between the stacking structures is divided into cell regions. The gate dielectric layers are respectively formed in one of the cell regions, and cover opposing sidewalls of the stacking 10 structures and sidewalls of the isolation pillars. The channel layers respectively cover an inner surface of one of the gate dielectric layers.

Abstract: A wall-mounted assembly may include one or more host devices which receive line voltage and generate low voltage power on one or more contacts for powering one or more modular devices. The one or more modular devices may be installed adjacent to the host device and may share a faceplate with the host device, such as a standard decorator faceplate. The modular devices may receive power from the host device via a power bus between the host device and the one or more modular devices. Further, the power bus may include a communication bus for communication between the host device and the modular devices. The faceplate may be a smart faceplate, which may include circuitry, such as a battery backup, occupancy sensing, a charging dock for a mobile phone, etc.

Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.