Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.

Abstract: An image forming apparatus includes a control unit. In a case where a total amount of liquid discharged from all of at least one liquid discharge head connected to one or more channel pipelines communicating with a tank until a predetermined first time period elapses from a first time is a first discharge amount and a total amount of liquid discharged from all of the at least one liquid discharge head connected to the one or more channel pipelines until the first time period elapses from a second time later than the first time by the first time period is a second discharge amount, the control unit is configured to adjust the discharge amount from a time later than the second time by the first time period, based on a value obtained by subtracting the second discharge amount from the first discharge amount.

Abstract: Filter media comprising surface-treated fiber webs having one or more advantageous physical properties are generally described. Certain improvements in the surface-treated fiber webs described herein may be realized in filter media comprising nanofiber layers. The improvements herein are, in some embodiments, related to favorable distributions of cavities in surface-treated fiber webs, such as those used in backers of the filter media.

Abstract: A package structure is provided, and includes an interposer, a control unit, a plurality of computing units, a signal transmission layer, and an electric-optical material. The control unit is bonded to the interposer. The computing units are disposed around and connected to the control unit. The signal transmission layer is formed in the control unit and the computing units. The electric-optical material is formed in the control unit and the computing units, and the electric-optical material overlaps the signal transmission layer.

Abstract: In one aspect of the present disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes a first conductive structure extending in a first direction, the first conductive structure coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed over, in a third direction perpendicular to the first direction and the second direction, the first conductive structure; and a via structure disposed over the second conductive structure and in contact with the dielectric material, wherein the dielectric material is configured to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

Abstract: A method of manufacturing a memory array includes forming a first bit-line stack over a substrate, forming a first data storage structure, and forming a word line. The method of forming the first bit-line stack includes forming a first bit line over the substrate, and blocking a portion of a top surface of the first bit line and a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure is formed to cover the top corner of the first bit line. The word line is formed to cover a sidewall of the first data storage structure.

Abstract: An information processing device is provided. The information processing device 20 includes a receiving part 452 configured to receive: paper jam occurrence information about a paper jam that has occurred in an image forming device 30; and sensor output log data associated with one or a plurality of sensors provided in the image forming device 30 to detect paper jam removal tasks performed in response to occurrence of the paper jam. The information processing device 20 includes a memory part configured to store procedural task data 354, in which one or a plurality of procedural tasks for removing the paper jam are described. The information processing device 20 includes an output control part 460 configured to output a task analysis result obtained based on: the procedural task data associated with the paper jam occurrence information; and the sensor output log data.

Abstract: A user equipment (UE) executes a semi-static channel access method in an unlicensed band. The UE receives a configured grant scheduling for multiple uplink (UL) transmissions over one or more fixed frame periods (FFPs), wherein the UL transmissions are referred to as configured grant (CG) UL transmissions. The UE derives, for each configured grant UL transmission of the configured grant UL transmissions, a channel occupancy time (COT) initiator of the configured grant UL transmission. The UE determines one or more transmission symbols for each of the configured grant UL transmissions according to the derived COT initiator. The UE transmits each of the configured grant UL transmissions in the one or more transmission symbols of the one or more FFPs.

Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

Abstract: In some examples, a computing device includes a first video interface for a first monitor, a second video interface for a second monitor, and a processor. In some examples, the processor obtains a first monitor identification from the first monitor and obtains a second monitor identification from the second monitor. In some examples, the processor sends the first monitor identification and the second monitor identification to a color profile server. In some examples, the processor receives a first color profile and a second color profile from the color profile server. In some examples, the processor causes the first color profile and the second color profile to install on the computing device.

Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

Abstract: In an operation control method of an integrated control apparatus for an autonomous driving vehicle, when a steering operation is performed on both of a first joystick lever and a second joystick lever to return to neutral positions after the steering operation, a lever which is always pivoted in an adduction direction is set to a function activation state, or a lever set to the function activation state during the steering operation is continuously maintained in the function activation state until the return to the neutral position is completed after the steering operation. In the present way, a user can more easily recognize the joystick lever in the function activation state.

Abstract: A semiconductor device includes a substrate having a first active region disposed in a first region of a substrate and a second active region disposed in a second region of the substrate. A first gate stack is disposed over the first active region and a second gate stack is disposed over the second active region, the first and second gate stacks having elongated shapes oriented in a first direction. A first metal layer is disposed over the first gate stack and the second gate stack. The first metal layer includes first metal layer structures oriented in a second direction orthogonal to the first direction. A second metal layer disposed over the first metal layer. The second metal layer includes second metal layer structures oriented in the first direction. A third metal layer is disposed over the second metal layer. The third metal layer includes a third metal layer structures oriented in the second direction.

Abstract: A battery management method includes obtaining a voltage-capacity profile in response to charging or discharging of a battery and diagnosing the state of the battery using an nth-order differential value (n being a natural number of 1 or greater) at at least one predetermined characteristic point obtained from an nth-order differential profile of the voltage-capacity profile.

Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell or ii) a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.

Abstract: A method for a semiconductor manufacturing process includes circulating a solution from a tank using a pump and receiving the solution from the pump at an inlet of a valve. When a manufacturing operation occurs, the solution is directed to a first outlet of the valve that is connected to a nozzle used in the manufacturing operation. When the manufacturing operation is idle, the solution is directed to a second outlet connected to a recirculation path; and recirculated back to the tank via the recirculation path for re-use in the manufacturing operation.

Abstract: To perform three-dimensional measurement of an object with high accuracy, a dot pattern is generated by a determination process of determining a reference position according to a rule defined by a Poisson disk sampling algorithm, a selection process of selecting one of a plurality of arrangement patterns indicating at least one or more dot arrangements, an arrangement process of arranging dots based on the arrangement pattern selected for the reference position, and an iterative process of performing the above processes a plurality of times, a projection device is controlled to project projection light including the dot pattern onto the object, an image capturing device is controlled to image-capture the object onto which the projection light is projected from two directions to acquire two captured images, parallax information is calculated about the acquire two captured images, and a three-dimensional shape of the object is specified based on the calculated parallax information.

Abstract: A semiconductor device includes a first and a second semiconductor fins extending along a first direction; an isolation region disposed between respective lower portions of the first and second semiconductor fins; a dielectric structure disposed between the first and the second semiconductor fins and above the isolation region, with a bottom surface aligned with a top surface of the isolation region; a gate isolation structure vertically disposed above the dielectric structure; and a metal gate layer extending along a second direction perpendicular to the first direction. The metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a top portion vertically extending above the dielectric structure and a bottom portion extending into the dielectric structure.

Abstract: The present disclosure describes an apparatus. The apparatus includes a chuck for placing an object thereon, a gas passage extending along a periphery of an outer sidewall of the chuck and separating the chuck into an inner portion and a sidewall portion, and a plurality of gas holes through the sidewall portion and configured to connect a gas external to the chuck to the gas passage.

Abstract: A method of forming a semiconductor structure includes the following steps. An antenna pad is formed. A plurality of conductive vias are formed over the antenna pad to electrically connect to the antenna pad, wherein the conductive vias are arranged to surround an area of the antenna pad. A plurality of first conductive patterns are formed over the conductive vias, to form a ground plane, wherein the first conductive patterns are overlapped with the area of the antenna pad and electrically isolated from the conductive vias.