Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate adjacent the semiconductor layer, epitaxially growing an active semiconductor device layer above the semiconductor layer and accumulated non-semiconductor atoms after the selective etching, and forming at least one circuit in the epitaxially grown active semiconductor device layer.

Abstract: A patterning process is performed on a semiconductor wafer coated with a bottom layer, a middle layer and a photoresist layer having a starting thickness. The patterning process includes: performing an exposure step including exposing the semiconductor wafer using a mask that includes a feature which produces an intermediate light exposure in a target area followed by processing that creates openings in the photoresist layer in accordance with the mask and thins the photoresist in the target area due to the intermediate light exposure in the target area leaving thinned photoresist in the target area; performing middle layer etching to form openings in the middle layer aligned with the openings in the photoresist layer, wherein the middle layer etching does not remove the middle layer in the target area due to protection provided by the thinned photoresist; and performing trim etching to trim the middle layer in the target area.

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate and forming a floating additive layer comprising a floating additive polymer. The floating additive polymer includes a pendant fluorine substituted organic group and one or more of a pendant acid generating group, a pendant base group, a pendant acid labile group, a pendant chromophore group, a pendant developer solubility promoter group, and a pendant acid diffusion control group. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern. The latent pattern is developed to form a pattern in the photoresist layer.

Abstract: A method for forming an array of nanostructures is presented.

Abstract: A dividing method of a wafer includes cutting a front surface of the wafer to a predetermined depth with a cutting blade to form bottomed cut-grooves, applying a water-soluble liquid resin to the front surface of the wafer and drying the water-soluble liquid resin to fill the cut-grooves with the resulting dried water-soluble resin, grinding the wafer at the back surface thereof with grinding stones, so that the cut-grooves are allowed to appear in the back surface of the wafer and the wafer is divided into individual chips, and ejecting rinse water against the wafer, which has been divided into the chips, to remove the water-soluble resin.

Abstract: Apparatuses for rapid-cycle high-temperature heating and cooling are disclosed. The apparatuses can be used for elementary, binary, tertiary, and quaternary alloys of wide and ultra-wide band gap compound semiconductors. The apparatuses can be used for wafer annealing, and can include an induction coil, and at least one gas nozzle. A susceptor holds a workpiece with a first face of the workpiece exposed and a second face of the workpiece in thermal contact with a first surface of the susceptor. The first gas nozzle is arranged to disperse cooling gas to the susceptor and workpiece assembly. Each heating operation uses inductive coupling to the susceptor to heat the workpiece from 800° C.-1100° C. to 1400° C.-2500° C. in about one second (for one example). Each cooling operation uses cooling gas dispersion to cool the workpiece from 1400° C.-2500° C. to 800° C.-1100° C. in about one second (for another cooling example).

Abstract: A tray 1 for large-size semiconductor integrated circuits comprises one or a plurality of pockets 2 for accommodating large-size semiconductor integrated circuits is provided. On the inner bottom surface 4 of each of the pockets, a rounded recess 10 having a circular outline 8 is formed. The circular outline 8 is generally concentric with the center of each of the pockets. The rounded recess 10 formed on the inner bottom surface 4 of a pocket 2 prevents the inner bottom surface 4 from contacting terminals on the bottom face of a semiconductor integrated circuit to be placed in the pocket.

Abstract: A substrate processing method including: a first assembly process of positioning a first substrate at a first position among the first position, a second position, a third position, a fourth position, and a fifth position; a second assembly process of positioning a second substrate at the second position by combining a second arrangement with a substrate group; a third assembly process of positioning a third substrate at the third position by combining a third arrangement with the substrate group; a fourth assembly process of positioning a fourth substrate at the fourth position by combining a fourth arrangement with the substrate group; and a fifth assembly process of positioning a fifth substrate at the fifth position by combining a fifth arrangement with the substrate group.

Abstract: There is provided a method of manufacturing a semiconductor device. The method includes forming a plurality of wires on an insulating layer, forming a sacrificial layer between the plurality of wires, forming a cover layer on the plurality of wires and the sacrificial layer, and removing the sacrificial layer formed below the cover layer by using mild plasma having a plasma damage rate to the insulating layer of 0.01 to 0.1 ?/s.

Abstract: A method of operating an electronic device that is configured to support manufacturing a semiconductor device includes (i) selecting a height of a stage of the electronic device that is configured to hold the semiconductor device, (ii) generating white light by using a light source of the electronic device, (iii) generating light of a selected wavelength by filtering the white light using a monochromater of the electronic device, (iv) emitting the light of the selected wavelength to the semiconductor device using a beam splitter of the electronic device, and (v) capturing reflection light reflected from the semiconductor device using a camera of the electronic device.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip and including a through-silicon via electrically connecting a front pad and a rear pad, a dielectric layer having a first region covering a side surface of the second semiconductor chip and a second region filling space between the first semiconductor chip and the second semiconductor chip, a first through-via penetrating through the first region of the dielectric layer, and a second through-via penetrating through the second region of the dielectric layer.

Abstract: An electronic module includes: a first board; a chip disposed on the first board and having a main electrode and a control electrode on a surface thereof on a side opposite to a surface thereof on a first board side; a power chip connection terminal disposed on the main electrode and being electrically connected to the main electrode; and a signal chip connection terminal having a columnar shape disposed on the control electrode and being electrically connected with the control electrode.

Abstract: A power generation planning method for a fuel cell device according to the present disclosure includes: receiving a power generation plan for a fuel cell device; storing the received power generation plan for the fuel cell device; and if a next power generation plan is not received and a remaining period of the stored power generation plan is shorter than a predetermined period, using data of the stored power generation plan to add a power generation plan so that the remaining period of the power generation plan is equal to or longer than the predetermined period.

Abstract: A method of improving an interface between an electrode and an electrolyte of an electrochemical cell is disclosed. The method includes forming an electrolyte material on an electrode of an electrochemical cell. The electrolyte may include a perovskite material. The electrolyte material may be exposed to one or more of an acid solution, a plasma, thermal shock, and gamma radiation to increase the surface roughness of the electrolyte material. Additional methods, electrochemical cells, and systems are disclosed.

Abstract: A battery system includes an anode circuit configured to urge a flow of anolyte therethrough to an anode side of an electrode and a cathode circuit configured to urge a flow of catholyte therethrough to a cathode side of the electrode. An electric circuit is operably connected to the electrode to utilize electrical energy generated via a chemical reaction between the flow of anolyte and the flow of catholyte at the electrode. The flow of anolyte is driven through the anode circuit by thermal expansion and/or thermal contraction of one or more components of the anode circuit. The flow of catholyte is driven through the cathode circuit by thermal expansion and/or thermal contraction of one or more components of the cathode circuit.

Abstract: A cylindrical battery and an electric apparatus, including an electrode assembly. The electrode assembly includes a positive electrode plate, a separator, and a negative electrode plate stacked and wound together. The positive electrode plate includes a positive current collector. The positive current collector has a first surface, the first surface is provided with an active material layer, an insulation layer, and an uncoated foil area arranged in order along an axial direction of the cylindrical battery. The electrode assembly further includes a flattened part, the flattened part being formed by bending and overlapping the uncoated foil area towards a central axis of winding of the electrode assembly and having a flattened surface. The insulation layer provides support for the positive current collector, preventing a short circuit caused by the flattened part folding over to exceed the separator and contact the negative electrode plate.

Abstract: According to embodiments of the present disclosure, an electrolyte for a secondary battery includes: a polymer matrix; and inorganic particles which contain boron and nitrogen, and have a two-dimensional shape, wherein a content of the inorganic particles is a content of the polymer matrix or more based on the weight. The secondary battery includes a cathode, an anode, and an electrolyte layer which is disposed between the cathode and the anode, and includes the above-described electrolyte for a secondary battery.

Abstract: Provided is a non-aqueous electrolyte including a lithium salt, an organic solvent, a compound represented by Formula 1 as a first additive, and a compound represented by Formula 2 as a second additive: wherein in Formulae 1 and 2, all the variables are described herein.

Abstract: A battery pack can comprise a battery monitoring system that can monitor a battery metric of a battery cell of a battery system cluster board, in response to a determination that the battery metric satisfies a first bypass condition, enables a bypass mode applicable to the battery system cluster board, and in response to a determination that the battery metric no longer satisfies the first bypass condition, exits the bypass mode. A primary controller can in response to a determination that a second bypass condition applicable to the battery system cluster board has been satisfied, sends an instruction to the battery monitoring system to enter the bypass mode, and in response to a determination that the second bypass condition is no longer satisfied, sends an override instruction to the battery monitoring system to exit the bypass mode.

Abstract: An interwoven voltage sense harness of a battery is provided. A battery system can include cells arranged in an array. The battery system can include a harness. The harness can include a circuit electrically insulated by a material. The harness can extend along a side of the cells. The harness can include a trace. The trace can be electrically coupled to the circuit. The trace can contact each of the cells to measure voltage of the cells. At least one aspect is directed to a method. The method can include providing a battery system comprising a plurality of cells arranged in an array and a harness.