Abstract: An apparatus, method, and program product for optimizing core performance and power in a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

Abstract: A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.

Abstract: A method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes forming pillars with a doped silicon region on the substrate. An electrically conductive gate material is deposited between and over the pillars. The gate material is etched such that the gate material partially fills a space between the pillars. The pillars are then etched such that a pair of pillars from the pillars include an insulating material over the doped silicon region. A gate contact is deposited between the pair of pillars such that the gate contact electrically couples the gate material at a contact interface level, and the insulating material extends below the contact interface level.

Abstract: This invention relates to updating an operating system in a hypervisor comprising: determining a new version of a component of the operating system; installing the new component version; measuring an identifying characteristic of the component and making it available to an attestation system; notifying the attestation system that a component has been updated to a new version whereby, when the attestation system finds that the identifying characteristic of the new component does not match a pre-stored attestation value it is aware that a legitimate mis-match could have occurred. The installing of the new version of the component comprises: identifying an updater associated with new version of the component; measuring an identifying characteristic of the identified updater; loading and installing the new version of the component; and making both the identifying measurement of the updater and the new version of the component available to the attestation system.

Abstract: A static analysis for identification of permission-requirements on stack-inspection authorization systems is provided. The analysis employs functional modularity for improved scalability. To enhance precision, the analysis utilizes program slicing to detect the origin of each parameter passed to a security-sensitive function. Furthermore, since strings are essential when defining permissions, the analysis integrates a sophisticated string analysis that models string computations.

Abstract: A search result is re-ranked/re-ordered in a user-specific manner, where the search result comprises an ordered sequence of identifications of a plurality of network-accessible documents that match a search query, based on a model corresponding to a user who will view the search result. The model comprises keywords and relationships among them, according to how the user perceives relationships among the keywords. The re-ranking comprises changing an order of at least one of the identified plurality of network-accessible documents within the ordered sequence, responsive to comparing ones of the keywords in the model to the identifications of network-accessible documents. The search result is then rendered, as re-ranked, for the user. The relationships may have an associated bond strength, and the re-ranking comprises changing the order accordingly. Keywords from the model are preferably used to group the identifications during the re-ranking.

Abstract: Disclosed is a semiconductor-on-insulator (SOI) structure (e.g., an SOI field effect transistor (FET)) and method of forming the SOI structure so as to have sub-insulator layer void(s) selectively placed so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device and the second section may contain a second device. Alternatively, the first and second sections may comprise different regions of the same device. For example, in an SOI FET, sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate.

Abstract: Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.

Abstract: Mobile network services are performed in a mobile data network that includes a radio access network and a core network. A breakout component in the radio access network breaks out data coming from a basestation connected to user equipment, and hosts edge applications that perform one or more mobile network services at the edge of the mobile data network. When a breakout component is not running a needed edge application, and the needed edge application is running in a neighboring basestation, the breakout component can route the request for the needed edge application to the neighboring basestation via the overlay network. The neighboring basestation processes the request using the needed edge application, then returns the data to the original basestation via the overlay network. The original basestation thus maintains the subscriber session with the user equipment while offloading the work of the needed application to a neighboring basestation.

Abstract: A method for automatically navigating potential websites for predictive browsing based on user activities along with efficiency of verifying content updates. A Uniform Resource Locator (URL) of websites and its associated attributes that a user visits can be recorded and stored in a storage engine. The potential sites can be predicted by a predictive engine component based upon a past browsing history and various environmental factors that are recorded in the storage engine. A dynamic content detection engine component examines each potential websites and detects if the site has been updated. The predictive engine enables the user to navigate to the potential websites thereby permitting the user to browse websites faster.

Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided.

Abstract: Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

Abstract: A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.

Abstract: In one embodiment, a data storage system includes a head; a drive mechanism for passing a medium over the head; a controller electrically coupled to the head; logic encoded in or available to the controller for: periodically determining a stopwrite threshold based on a standard deviation or a variance at a current position error signal sample, wherein a smoothing factor applied to a subsequent calculation of the standard deviation or variance is altered based at least in part on a current magnitude of the standard deviation or the variance; determining whether the current position error signal sample exceeds the stopwrite threshold; disabling writing when the current position error signal sample exceeds the stopwrite threshold; and enabling writing when the current position error signal sample does not exceed the stopwrite threshold. Other systems, methods, and computer program products are described according to more embodiments.

Abstract: Techniques for providing session level replication and fail-over as a network service include generating a replication rule that replicates network traffic destined for a primary server from an originating server to a network controller and installing said rule in a switch component, identifying flows from the originating server to the primary server, replicating each incoming data packet intended for the primary server to the network controller for replication and forwarding to replica servers, determining said primary server to be in a failed state based on a number of retransmissions of a packet, to selecting one of the replica servers as a fail-over target, and performing a connection level fail-over by installing a redirection flow in the switch component that redirects all packets destined to the primary server to the network controller, which forwards the packets to the replica server and forwards each response from the replica server to said originating server.

Abstract: A method of reducing white bump formation and dielectric cracking under controlled collapse chip connections (C4s). The method comprises fabricating a substrate having a plurality of metallization layers, one or more of the layers is of low k dielectric material. The substrate includes a plurality of attachment pads for the C4s. The fabricating comprises selectively forming at least a portion of the substrate with metal fill having a higher Young's modulus of elasticity than any of the one or more layers of low k dielectric material in portions of the substrate located beneath at least some of the attachment pads.

Abstract: Embodiments relate to reducing a number of read ports for register pairs. An aspect includes executing an instruction. The instruction identifies a pair of registers as containing a wide operand which spans the pair of registers. The executing of the instruction includes determining whether a pairing indicator associated with the pair of registers has a first value, a second value or a third value. Based on the pairing indicator having the first value, the wide operand is read from the wide register. Based on the pairing indicator having the second value the wide operand is read from the pair of registers. Based on the pairing indicator having the third value, the wide operand is speculatively read from a predetermined register. The predetermined register consists of the wide register or the pair of registers.

Abstract: Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

Abstract: A method for managing objects stored in a shared memory cache. The method includes accessing data from the shared memory cache using at least a plurality of cache readers. A system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.

Abstract: An embodiment of the invention provides a method for source control in a computer program, wherein the computer program includes a plurality of files for execution of a plurality of processes. A revised process that is selected by a user on a graphical user interface is identified, wherein the revised process includes an execution path. A revised portion of a file in the revised process that the user is revising, has revised, and/or is planning on revising is identified. Portions of files that are in the execution path of the revised process are identified. The portions of the files in the execution path of the revised process are locked with a source control processor. The locking disallows revisions (e.g., write and delete operations) to the portions of the files in the execution path of the revised process that are not made by the user.