Abstract: A PLL circuit includes a phase comparator, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, a frequency difference determination unit, and an FV characteristics adjustment unit. The frequency difference determination unit determines whether or not a frequency difference between a feedback oscillation signal and an input signal is equal to or smaller than a threshold value. The FV characteristics adjustment unit selects a frequency band in the voltage-controlled oscillator and adjusts FV characteristics.

Abstract: The present invention relates to a video signal transmission device and the like that can support a variety of system specifications. The device includes a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals having a packet configuration of size corresponding to the number of pixels and the number of tone bits of a color signal constituting a video signal. At this time, a control signal including a pulse having a width corresponding to the number of pixels and the number of tone bits is also generated. The encoder unit applies encoding processing having encoding efficiencies that are different between a first period and a second period of a control signal that are distinguished depending on existence or non-existence of a pulse to the block signals.

Abstract: A transmission/reception system includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P111 and P112that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P111 and P112 is constant over a state where no electric power is supplied and an idle state.

Abstract: The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20n, based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.

Abstract: A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.

Abstract: Disclosed herein are a data transmission circuit and a data communication device that transmit data using an Alternating Current (AC)-coupled transmission line. The data transmission circuit includes a data transmission unit for transmitting data via a transmission line having a single AC-coupled line or a plurality of AC-coupled lines. When transmitting data, the data transmission unit transmits the data via the transmission line by sequentially setting a first electric potential corresponding to the data and a second electric potential different from the first electric potential. When transitioning from data transmission mode to an idle state, the data transmission unit sets an intermediate electric potential between the first electric potential and the second electric potential.

Abstract: A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

Abstract: A clock data restoration device (1A) includes a sampler portion (11), a phase comparison portion (12), a drive portion (13), a charge pump (14), a capacitive element (15), a potential adjustment portion (16) and a voltage control oscillator (17). The phase comparison portion (12) outputs a signal (UP) that becomes a significant value when the phase of a clock (CKX) delays with respect to an input digital signal, and outputs a signal (DN) that becomes a significant value when the phase advances. The drive portion (13) increases or decreases a value ? to or from a variable ? when the signals (UP) and (DN) become a significant value, and increases or decrease a value N to or from the variable ? when the value of the variable ? is equal to or more than +N or when the value of the variable ? is equal to or less than ?N, and signals (UPFRQ) and (DNFRQ) are output to the charge pump (14).

Abstract: Disclosed herein is a sigma-delta modulator, including an integration circuit, a first DAC unit, and a second DAC unit. The integration circuit includes first and second terminals, and integrates a voltage supplied via the first terminal. The first DAC unit alternately supplies a first voltage obtained at one end of a first resistor to the first terminal and the second terminal. The second DAC unit alternately supplies a second voltage at the other end of a second resistor to the second terminal or the first terminal. The second DAC unit supplies the second voltage to the second terminal when the first DAC unit supplies the first voltage to the first terminal. The second DAC unit supplies the second voltage to the first terminal when the first DAC unit supplies the first voltage to the second terminal.

Abstract: When the value of a power supply voltage (VDD) becomes a first threshold value or higher, a first start-up circuit (20) causes a band gap reference circuit (10) to start a stable operation and a first voltage value (VA) is output from the band gap reference circuit (10). When the value of the power supply voltage becomes a second threshold value or higher which is greater than the first threshold, a second start-up circuit (40) turns on a PMOS transistor (MP3) of a voltage dividing circuit (30), and a second voltage value (VB) output from the voltage dividing circuit (30) becomes a value, which is derived by dividing the value of the power supply voltage according to the resistance ratio of resistors (R31, R32). From a voltage comparison circuit (50), a reset level voltage value is output when the second voltage value (VB) is smaller than the first voltage value (VA), and a power-supply voltage level voltage value is output if the second voltage value (VB) becomes the first voltage value (VA) or higher.

Abstract: In a PLL frequency synthesizer, a loop is constituted by a phase comparison unit, a gate unit, a charge pump, a capacitive element, a potential adjustment unit, a voltage-controlled oscillator, and a feedback division unit. In this loop, the gate unit and the charge pump are provided in parallel with the potential adjustment unit. A charging/discharging current is input from the charge pump to the capacitive element and the potential of a first end of the capacitive element is adjusted by the potential adjustment unit, so that a phase difference between a reference oscillation signal and a feedback oscillation signal input to the phase comparison unit is small.

Abstract: An image signal processing device 1 comprises an encoding part 10, a delay part 20, a difference calculation part 30, a decoding part 40, a quantization error determination part 50 and a corrected image data output part 60.

Abstract: A DC-DC converter 1 is provided with a voltage conversion unit 100 and a control unit 200. The control unit 200 includes: a comparator 20 and a trigger signal generation section 30 which generate a trigger signal when an output voltage is reduced from a reference voltage after having received a minimum off-time signal, a DLL section 40 generating a reference delay signal, a delay section 50 generating delay signals which are delayed from the trigger signal by a predetermined amount, further delayed by an on-time, still further delayed by a second dead time, and yet still further delayed by a minimum off-time, respectively, according to the reference delay signal, and a timing control section 60 determining a start time point and an end time point of an on-pulse, a start time point and an end time point of an off-pulse and also generating a minimum off-time signal, according to these delay signals.

Abstract: Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

Abstract: A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.

Abstract: An image signal processing device 1 comprises a delay part 10, a basic correction value output part 20, and a corrected image data output part 30. To the basic correction value output part 20, data G1[7:4] of high order 4 bits of image data G1[7:0] of a first frame to be output from the delay part 10 is input and data G2[7:4] of high order 4 bits of image data G2[7:0] of a second frame to be input to the delay part 10 is input, and the basic correction value output part 20 outputs basic correction values D1 to D4 corresponding to the data. To the corrected image data output part 30, G1[7:0], G2[7:0] and D1 to D4 are input, and the corrected image data output part 30 performs when “G1[7:4]=G2[7:4]” holds and performs different processing when “G1[7:4]?G2[7:4]” holds, and acquires corrected image data G2?[7:0] corresponding to data (G1[7:0], G2[7:0]) by interpolation calculation.

Abstract: (Problem) To provide a switching power source having a stable negative voltage output. (Means for Solving the Problem) A switching power source according to the present invention comprises a switching power source controller including a soft start circuit; an output stage including a coil, a switching device, driven by an output from the switching power source controller, for controlling a current flowing in the coil, and a diode having an anode connected to an output terminal and a cathode connected to a connection point between the switching device and the coil; a voltage dividing circuit for dividing an output voltage from the soft start circuit and a voltage at the output terminal; and a soft start period adjustment circuit for adjusting a soft start period.

Abstract: A signal conversion circuit 2 according to an embodiment of the present invention has a difference amplifier 10 and a source follower 20. The difference amplifier 10 has first and second resistors 11, 12 connected in series, third and fourth resistors 13, 14 connected in series, first and second PMOS transistors 15, 16, and a current source 18. The source follower 20 has first and second NMOS transistors 22, 24. A source of the first NMOS transistor 22 is connected between the first and second resistors 11, 12, while a source of the second NMOS transistor 24 is connected between the third and fourth resistors 13, 14.

Abstract: In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.

Abstract: The comparator-system DC-DC converter 1 comprises the voltage conversion section 100 and the control unit 200. The control unit 200 comprises comparator sections 20 and 40 which compare the output voltage of the voltage conversion section 100 and the reference voltage, and determine a predetermined ON width of the ON pulse or the OFF width of the OFF pulse of the control signal Ssw, and a counter section 60 which counts at least either one of the ON pulses and OFF pulses of the control signal and counts the reference clocks to adjust the predetermined ON width so that the ratio between the count value of the control signal Ssw and the count value of the reference clock is M:N where M and N are natural numbers.