Abstract: An equalizer adjusting device includes a comparator, an inequality counter, an adjuster, and the like. The comparator performs magnitude comparison between a voltage value Vout of each bit output from an equalizer and a threshold value MonLVL and outputs a logical value MonSMP according to a result of the comparison. The inequality counter inputs a logical value DatSMP output from a sampler in accordance with the result of magnitude comparison between the voltage value Vout of each bit and a reference value, and the logical value MonSMP output from the comparator and counts events in which the logical value DatSMP and the logical value MonSMP differ from each other, every period. The adjuster adjusts a gain of the equalizer and the threshold value MonLVL of the comparator based on a counted value of the inequality counter.

Abstract: A duty compensation device of one embodiment has a structure capable of more accurately setting a duty of a clock within an appropriate range. The duty compensation device comprises a duty adjusting unit, a duty measuring unit, a controlling unit. The duty measuring unit generates a sampling clock of a frequency fn that is asynchronous to the clock over an n-th period Tn (n=1 to N and N is an integer of 3 or more), and obtains measurement information for specifying the duty of the clock by using the sampling clock. The controlling unit determines a control code to be given to the duty adjusting unit based on control code candidates obtained for each of the N periods T1 to TN and the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.

Abstract: A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a first power supply line DL1 of the first circuit 1, a second terminal T2 that applies a second potential to a second power supply line DL2 of the second circuit 2, a third terminal T3 that is connected to a signal transfer line of the first circuit 1, and a protection circuit that is connected to the third terminal T3, and discharges a current from the third terminal T3 to a fourth terminal T4 when a potential of the third terminal T3 becomes higher than a first threshold value. The first power supply line DL1 and the second power supply line DL2 are separated, and the fourth terminal T4 is not directly connected to the first power supply line DL1 and is electrically connected to a lead.

Abstract: A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines during a period during which a pulse output instruction signal is at a significant level; and a detector that outputs a detection result signal indicating a magnitude relationship between a voltage level of the common-mode pulse and a threshold, during a period during which the pulse output instruction signal is at a significant level, and outputs a detection result signal indicating that the voltage level of the common-mode pulse does not exceed the threshold, during a period during which the pulse output instruction signal is at a non-significant level.

Abstract: A PLL circuit of one embodiment has a structure for preferably setting the FV characteristic of an LC-VCO. The PLL circuit includes a voltage controlled oscillator, a phase comparator, a charge pump, a loop filter, and an FV characteristic adjustment unit setting the FV characteristic. The voltage controlled oscillator has an FV characteristic indicating the relationship between a control signal and a frequency and outputs an oscillation signal having a frequency corresponding to the control signal based on the FV characteristic. The phase comparator detects a phase difference between an input signal and the control signal. The charge pump outputs a corrected voltage value changed according to the phase difference. The loop filter outputs a control voltage value changed in response to corrected voltage value variations. The FV characteristic adjustment unit generates an FV characteristic control signal by a mean corrected voltage value.

Abstract: A duty compensation device of one embodiment has a structure capable of more accurately setting a duty of a clock within an appropriate range. The duty compensation device comprises a duty adjusting unit, a duty measuring unit, a controlling unit. The duty measuring unit generates a sampling clock of a frequency fn that is asynchronous to the clock over an n-th period Tn (n=1 to N and N is an integer of 3 or more), and obtains measurement information for specifying the duty of the clock by using the sampling clock. The controlling unit determines a control code to be given to the duty adjusting unit based on control code candidates obtained for each of the N periods T1 to TN and the control code candidates in which the duty specified by measurement information obtained by the duty measuring unit is within a predetermined range.

Abstract: The present embodiments relate to a reception device that enables accurate separation of video data and SYNC data sent out from a transmission device in accordance with a data enable (DE) signal, from among reception data even if the reception data deteriorates due to noise. The reception device separates the video data and the SYNC data from the reception data in accordance with the DE signal reproduced using a detection result of the BS data and the BE data representing a transition timing of a signal level of the DE signal and a prediction result of detection timings of the BS data and the BE data or a prediction result of the transition timing of the DE signal.

Abstract: A PLL circuit includes a phase comparator, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider, and a phase compensator 70. The loop filter 30 includes a resistor 31, a first capacitance element 32, and a second capacitance element 33. The phase compensator 70 is provided in parallel to the charge pump 20 and adds a differentiation term to an open-loop transfer function. The phase compensator 70 includes a buffer 71 receiving a phase difference signal output from the phase comparator and a third capacitance element 72 provided between an output terminal of the buffer 71 and an input terminal of the loop filter 30.

Abstract: The present invention relates to a video signal transmission device and the like that can support a variety of system specifications. The device includes a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals having a packet configuration of size corresponding to the number of pixels and the number of tone bits of a color signal constituting a video signal. At this time, a control signal including a pulse having a width corresponding to the number of pixels and the number of tone bits is also generated. The encoder unit applies encoding processing having encoding efficiencies that are different between a first period and a second period of a control signal that are distinguished depending on existence or non-existence of a pulse to the block signals.

Abstract: A first communication unit 21 of a host-side transceiver device 20 performs communication based on an I2C communication scheme with a host device 10 and receives an access request signal sent from the host device 10. A second communication unit 22 performs communication based on a communication scheme different from the I2C communication scheme with a remote-side transceiver device 30 and sends the access request signal received by the first communication unit 21 to the remote-side transceiver device 30. The first communication unit 21 notifies the host device 10 that the first communication unit 21 has received the access request signal sent from the host device 10 before the access to the remote device 40 based on the access request signal sent from the second communication unit 22 ends.

Abstract: A video signal transmission and reception system includes a video signal receiver in a video signal reception module, a video signal transmitter in a camera module, and a specific video signal transmitter in a specific camera module. In the specific camera module, a frame signal generated by a frame signal generator is sent to the video signal receiver from the specific video signal transmitter. The frame signal is sent to the video signal transmitters in a plurality of the camera modules from the video signal receiver.

Abstract: A video signal receiver includes a clock signal receiver, a frame signal generator, and a frame signal transmitter. The clock signal receiver receives a camera video signal clock sent from a video signal transmitter in a camera module and outputs the clock to the frame signal generator. The frame signal generator generates a frame signal based on the clock received by the clock signal receiver and outputs the frame signal to the frame signal transmitter. The frame signal transmitter receives input of the frame signal output from the frame signal generator and sends the frame signal to the video signal transmitter of each camera module.

Abstract: A video signal transmission and reception system includes a first video signal receiver and a second video signal receiver in a video signal reception module and a video signal transmitter in a camera module. The video signal reception module includes the first video signal receiver, the second video signal receiver, and a central operation processor. A frame signal generated in the first video signal receiver is sent to a video signal transmitter of a first group and is output to the second video signal receiver. In addition, the frame signal generated in the first video signal receiver is input into the second video signal receiver and is sent to a video signal transmitter of a second group from the second video signal receiver.

Abstract: A signal multiplexer according to the present embodiment has a configuration sufficiently capable of accelerating a data rate. The signal multiplexer includes M number of front units and a rear unit. An m-th front unit Am outputs an output signal corresponding to an m-th input signal Im when both the control signal Cm and the control signal Cn are significant levels, and outputs an output signal having a fixed level when at least either one of the control signal Cm or the control signal Cn is an non-significant level. A rear unit B receives signals from the front units, and outputs a signal having a different signal level in a case in which all the output signals from the front units are the same level or in the other case.

Abstract: Provided is a reception apparatus capable of shortening a time period until the original data and clock can be recovered from a digital signal after temporary superimposition of noise on the digital signal stops. A reception apparatus 20 includes a receiver unit 21, a voltage-controlled oscillator 22, a sampler unit 23, a control voltage generation unit 24, an error detection unit 25, a training control unit 26, and an equalizer control unit 27. The receiver unit 21 includes an equalizer unit 21A. When the error detection unit 25 detects an error of a digital signal, the reception apparatus 20 causes a phase/frequency comparison by the control voltage generation unit 24 to be stopped.

Abstract: A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instruction unit (17), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit (16) detects a phase difference between a first clock (CLK1) applied to the first latch unit (11) and a third clock (CLK3) applied to the second latch unit (12). The reset instruction unit (17) outputs a reset instruction signal (RSTn) to the frequency division unit (14) when the phase difference is not within a target range.

Abstract: The present invention relates to a video signal transmission device and the like that can support a variety of system specifications. The device includes a packer unit, an encoder unit, and a serializer. The packer unit generates, from a video signal of one or more pixels, a plurality of block signals having a packet configuration of size corresponding to the number of pixels and the number of tone bits of a color signal constituting a video signal. At this time, a control signal including a pulse having a width corresponding to the number of pixels and the number of tone bits is also generated. The encoder unit applies encoding processing having encoding efficiencies that are different between a first period and a second period of a control signal that are distinguished depending on existence or non-existence of a pulse to the block signals.

Abstract: A transmission/reception system includes a transmission device 10 and a reception device 20 that is connected to each other through differential signal lines 30 and a signal line 40, and receives a differential signal that is sent out from the transmission device 10 using the reception device 20. The transmission device 10 includes a signal output unit 11, a request input unit 12, and a resistor 13. The signal output unit 11 sends out a differential signal from a pair of output terminals P111 and P112that are connected to the differential signal lines 30. A common voltage of each of the pair of output terminals P111 and P112 is constant over a state where no electric power is supplied and an idle state.

Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.

Abstract: The embodiment relates to an input device comprises first and second MOS transistors, first to fourth resistors, and a comparator circuit. The first MOS transistor has a drain connected to a first terminal having a first voltage, a gate connected to a signal input terminal, and a source connected to a second terminal having a second voltage via the first and third resistors. The second MOS transistor has a drain and a gate connected to the first terminal, and a source connected to the second terminal via the second and fourth resistors. The comparator circuit outputs a signal having a level corresponding to a state in which a voltage of a node between the first and third resistors is higher or lower than a voltage of a node between the second and fourth resistors.