Abstract: (Problems) To realize a circuit capable of keeping a constant duty ratio of output isophase multiphase clock signals independently from the duty ratio of input clock signal while minimizing the increase of the number of devices and suppressing the increase of the circuit area of the semiconductor substrate and the increase of the power consumption. (Means for Solving the Problems) In an isophase multiphase clock signal generation circuit according to the present invention, an input clock signal is converted into a ½-frequency-divided complementary clock signal and then is input to a complementary voltage controlled delay device array. The input clock signal is ½-frequency-divided, and therefore becomes a clock signal having a constant duty ratio with no dependency on the duty ratio of the input clock signal.

Abstract: A semiconductor integrated circuit in which multiphase clock signals having the same phase difference are supplied from a multi-stage differential ring oscillator to other circuits, the multiphase clock signals can be prevented from being degraded in waveform due to electrostatic coupling between wirings of the multiphase clock signals and also wired in as small an area as possible. The semiconductor integrated circuit includes: multiple stages of amplifier circuits, connected in a ring form, for performing oscillating operation; a logic circuit for performing logic operation on the basis of predetermined ones of output signals of the multiple stages of amplifier circuits to output a plurality of clock signals having different phases from each other and duties not equal to 0.5; and a plurality of wirings for transmitting the plurality of clock signals output from the logic circuit.

Abstract: A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m?1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

Abstract: A semiconductor integrated circuit with stabilized amplitude and offset potential of output signals comprising an output circuit including plural transistors supplied with differential signals, for performing switching operation. A first transistor is connected between a first power supply potential and the output circuit. A second transistor is connected between the output circuit and a second power supply potential. A third transistor is connected to the first power supply potential. A fourth transistor, passes a current proportional to that flowing in the second transistor. A differential amplifier controls gate potentials of the first and third transistors such that a potential at a connection point between a first resistance and a second resistance approaches a predetermined potential.

Abstract: Provided is a circuit for implementing the coding of a DVI (Digital Visual Interface) standard in a small size of hardware, at high speed, and with low power consumption. In a DVI coding circuit, the input of a number-of-levels comparison circuit 22 for judging which of the number of bits at a level “H” and the number of bits at a level “L” is larger in the input signal of the coding circuit is set at 7 bits. The output of a number-of-transitions decrease circuit 23 for decreasing the number of the transitions between adjacent two bits can be inverted for 4 bits on the basis of the output of the number-of-levels comparison circuit 22. A DC balance circuit 24 for keeping the direct current-wise balance of the output signal of the coding circuit includes a 4-bit register 31, a number-of-levels difference computation circuit 27, a condition decision circuit 28, a bit inversion circuit 29 and an addition circuit 30.

Abstract: A differential circuit including a differential amplifier circuit having a differential element provided in a signal input circuit, a constant current source connected to the differential element, and loads respectively connected to the differential element, and a source follower circuit that outputs a differential voltage based on voltage drops developing across the loads, includes a current supply circuit that supplies a given current to the loads connected in series with the differential element when the differential element is off.

Abstract: A receiver apparatus having a demodulator circuit that demodulates transmitted serial data into parallel data by sampling the transmitted serial data on the basis of a first and a second clock signals having different numbers of clocks to be output in synchronization with a cycle of a transmitted clock includes a first synchronizing circuit that generates the first clock signal synchronized with the cycle of the transmitted clock, and a second synchronizing circuit that generates the second clock signal synchronized with the cycle of the transmitted clock and having a number of clocks different from the first clock signal.

Abstract: A semiconductor integrated circuit including a plurality of ADCs subjected to interleave-operation in parallel, or a semiconductor integrated circuit including an imaging ADC using a plurality of circuit elements to be switched sequentially, in which even when an image signal of any specification is input, an output signal of the plurality of ADCs or the imaging ADC is averaged to reduce irregularities on a screen. The semiconductor integrated circuit includes a plurality of analog/digital converting circuits (11) operated in parallel for sequentially converting an analog image signal to a digital image signal, a multi-phase clock signal generating circuit (12) for generating multi-phase clock signals to be used for periodically operating the plurality of analog/digital converting circuits (11) in a certain order, and a control circuit (20) for controlling the multi-phase clock signal generating circuit (12) to change a period or an order of operating the plurality of analog/digital converting circuits (11).

Abstract: A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

Abstract: [Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation. [Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

Abstract: In a semiconductor integrated circuit including a phase comparison circuit for a DLL in a reception circuit for receiving serial digital transmission signals, phase detection characteristics of the phase comparison circuit are improved while preventing false lock so as to improve response speed and locking accuracy of the DLL as a whole.

Abstract: A semiconductor integrated circuit including a plurality of ADCs subjected to interleave-operation in parallel, or a semiconductor integrated circuit including an imaging ADC using a plurality of circuit elements to be switched sequentially, in which even when an image signal of any specification is input, an output signal of the plurality of ADCs or the imaging ADC is averaged to reduce irregularities on a screen. The semiconductor integrated circuit includes a plurality of analog/digital converting circuits (11) operated in parallel for sequentially converting an analog image signal to a digital image signal, a multi-phase clock signal generating circuit (12) for generating multi-phase clock signals to be used for periodically operating the plurality of analog/digital converting circuits (11) in a certain order, and a control circuit (20) for controlling the multi-phase clock signal generating circuit (12) to change a period or an order of operating the plurality of analog/digital converting circuits (11).

Abstract: In a semiconductor integrated circuit including a phase comparator circuit for a PLL or DLL, overall lock precision of the PLL or DLL is improved by eliminating a dead zone of the phase comparator circuit and preventing output current offset of a charge pump circuit.