Abstract: This embodiment relates to a clock data recovering apparatus capable of improving CID resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.

Abstract: A receiving device includes a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.

Abstract: A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a first power supply line DL1 of the first circuit 1, a second terminal T2 that applies a second potential to a second power supply line DL2 of the second circuit 2, a third terminal T3 that is connected to a signal transfer line of the first circuit 1, and a protection circuit that is connected to the third terminal T3, and discharges a current from the third terminal T3 to a fourth terminal T4 when a potential of the third terminal T3 becomes higher than a first threshold value. The first power supply line DL1 and the second power supply line DL2 are separated, and the fourth terminal T4 is not directly connected to the first power supply line DL1 and is electrically connected to a lead.

Abstract: A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.

Abstract: A transmitter 1 comprises a clock generation portion 4, FIFO portion 6, and serial signal creation portion 7. The clock generation portion 4 performs modulation by spectrum spreading of a reference clock CKref, and generates a first clock CK1 with a high modulation factor and a second clock CK2 with a low modulation factor. The FIFO portion 6 takes as inputs the first clock CK1 which has been output from the clock generation portion 4 to a data generation portion 2 and output from the data generation portion 2, a parallel data signal which has been synchronized with the first clock CK1 in the data generation portion 2 and output, and the second clock CK2 output from the clock generation portion 4, and synchronizes the parallel data signal Pdata with the second clock CK2 and outputs the parallel data signal Pdata. The serial signal creation portion 7 converts a parallel data signal PRdata into a serial data signal Sdata.

Abstract: A transmission/reception system 1 includes a transmission device 10 configured to transmit image data and a reception device 20 configured to receive the image data transmitted from the transmission device 10. The transmission device 10 includes a serializer 11, an encoding unit 12, a data buffering unit 13, a data selection unit 14, a counter 15, and a synchronization signal generation unit 16. The data buffering unit 13 buffers data every n bits in synchronization with the clock. The data selection unit 14 outputs m-bit data selected from the data buffered by the data buffering unit 13 on the basis of a count value from the counter 15.

Abstract: A transmission/reception system 1 includes a transmission apparatus 10A, and a reception apparatus 20A. The transmission apparatus 10A includes a first switch 101, a second switch 102, a first transistor 111, a second transistor 112, a first differential amplifier 121, and a second differential amplifier 122. The reception apparatus 20A includes a first transistor 211, a second transistor 212, a first differential amplifier 221, a second differential amplifier 222, a first resistor 231, a second resistor 232, and a reception unit 240.

Abstract: The present embodiment relates to, for example, a transceiver system capable of notifying a transmission device of an asynchronous state of a reception device with a simple configuration. The reception device includes an input unit, a synchronous-state detector, a resistance-value controller, and a terminal resistor. When the synchronous-state detector detects the asynchronous state, the resistance-value controller sets a resistance value of the terminal resistor to a resistance value indicating the asynchronous state. The transmission device includes an output unit, an amplitude detector, an output controller, and a transmission resistor. The output controller causes the output unit to output a signal constituting normal data including clock information when the synchronous state of the reception device is detected, and causes the output unit to output a signal constituting training data including the clock information when the asynchronous state of the reception device is detected.

Abstract: The signal multiplexer 1 inputs two selection signals CLK<1>, CLK<2> that sequentially reach significant levels, inputs two input signals IN<1>, IN<2>, and outputs, from an output terminal 14, a signal OUT that depends on an m-th input signal IN<m> of the two input signals when an m-th selection signal CLK<m> of the two selection signals is at the significant level. The signal multiplexer 1 includes a resistance unit 20 and two drive units 301, 302. Each of the drive units 30m includes a driving switch 31m, a selecting switch 32m, and a potential stabilizing switch 33m. When one of the selecting switch 32m and the potential stabilizing switch 33m in each of the drive units 30m is in a closed state, the other is in an open state.

Abstract: Provided is a reception apparatus capable of shortening a time period until the original data and clock can be recovered from a digital signal after temporary superimposition of noise on the digital signal stops. A reception apparatus 20 includes a receiver unit 21, a voltage-controlled oscillator 22, a sampler unit 23, a control voltage generation unit 24, an error detection unit 25, a training control unit 26, and an equalizer control unit 27. The receiver unit 21 includes an equalizer unit 21A. When the error detection unit 25 detects an error of a digital signal, the reception apparatus 20 causes a phase/frequency comparison by the control voltage generation unit 24 to be stopped.

Abstract: For serial data transmitted from a transmission device 10 to a reception device 20, a timing of transition from a first level to a second level is in each unit period. Image data serves as a first type of data for which two or more transitions from the second level to the first level are in each unit period. Control data serves as a second type of data for which one transition from the second level to the first level is in each unit period and the number of bits having the second level in each unit period corresponds to a control signal.

Abstract: Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.

Abstract: A mode switching notification in a first mode is transmitted from a transmission device 10 to a reception device 20 according to a first protocol. In a second mode, training data is transmitted from the transmission device 10 to the reception device 20, clock training is performed in the reception device 20, and a mode switching notification for the first mode is transmitted from the transmission device 10 to the reception device 20 according to a second protocol simpler and faster than the first protocol.

Abstract: An imaging system 1 includes an imaging control device 10, an imaging device 20, and a light emitting device 30. The imaging control device 10 is provided for controlling the imaging device 20 and the light emitting device 30, and includes an evaluation unit 13, a light reception adjustment unit 14, and a light emission adjustment unit 15. The evaluation unit 13 evaluates respective brightnesses of the first image data and the second image data that are output from the imaging device 20. The light reception adjustment unit 14 adjusts any of an exposure time, a diaphragm value, and a gain that are to be used when the imaging device 20 captures an image, based on a brightness evaluation result. The light emission adjustment unit 15 causes the light emitting device 30 to emit light of either wavelength band of the first wavelength band and the second wavelength band, and adjusts a light emission intensity of the light, based on an evaluation result.

Abstract: A receiving device includes a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.

Abstract: A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.

Abstract: A clock data recovery device 1 generates a recovered clock Recovered Clock and recovered data Recovered Data based on an input signal Data In, and includes a signal selector 10, a phase delay unit 20, a time measurement unit 30, a phase selector 40, an edge detector 50, a polarity detector 60, a logic inverter 70, and a data output unit 80. The signal selector 10, the phase delay unit 20, the time measurement unit 30, and the phase selector 40 constitute a clock-generation device 1A. The phase delay unit 20 includes a plurality of cascaded delay elements 211 to 21P. The phase selector 40 selects a signal output from the delay element in a position corresponding to a unit interval time among the delay elements 211 to 21P, and outputs the signal as a feedback clock Feedback Clock.

Abstract: A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.

Abstract: The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20n, based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.

Abstract: A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.