Patents Assigned to Third Dimension (3D) Semiconductor, Inc.
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Publication number: 20120040521Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.Type: ApplicationFiled: October 25, 2011Publication date: February 16, 2012Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventor: Xingbi CHEN
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Patent number: 8071450Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer with a substrate of a first conductivity type and forming a first epitaxial layer of the first conductivity type on the substrate. The first epitaxial layer has a first thickness. The method further includes growing a first oxide layer on the first epitaxial layer, masking the first oxide layer, ion implanting to create at least one embedded region of a second conductivity type in the first epitaxial layer, removing the first oxide layer, and forming a second epitaxial layer of the first conductivity type on the first epitaxial layer. The second epitaxial layer has the first thickness minus a thickness equal to a thickness of the at least one embedded region of the second conductivity type.Type: GrantFiled: January 16, 2009Date of Patent: December 6, 2011Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Xing-Bi Chen
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Patent number: 7977745Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.Type: GrantFiled: September 4, 2008Date of Patent: July 12, 2011Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Fwu-Iuan Hshieh
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Patent number: 7772086Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: GrantFiled: March 21, 2008Date of Patent: August 10, 2010Assignee: Third Dimension (3D) Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Patent number: 7704864Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched into an active region of the substrate forming a plurality of mesas. A preselected area in the active region is oxidized and then etched using a dry process oxide etch to remove the oxide in the bottoms of the trenches. A protective shield is formed over a region at a border between the active region and the termination region. The protective shield is partially removed from over the preselected area. Dopants are implanted at an angle into mesas in the preselected area. The plurality of trenches are with an insulating material, the top surface of the structure is planarized and a superjunction device is formed on the structure.Type: GrantFiled: March 21, 2006Date of Patent: April 27, 2010Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Fwu-Iuan Hshieh
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Patent number: 7622787Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: GrantFiled: April 16, 2008Date of Patent: November 24, 2009Assignee: Third Dimension (3D) Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Brain D. Pratt
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Publication number: 20090130828Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.Type: ApplicationFiled: January 16, 2009Publication date: May 21, 2009Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventor: Xingbi Chen
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Patent number: 7504305Abstract: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.Type: GrantFiled: January 31, 2006Date of Patent: March 17, 2009Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Richard A. Blanchard
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Patent number: 7498614Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.Type: GrantFiled: August 14, 2007Date of Patent: March 3, 2009Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Xing-bi Chen
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Publication number: 20080315327Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.Type: ApplicationFiled: September 4, 2008Publication date: December 25, 2008Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventor: Fwu-Iuan Hshieh
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Publication number: 20080290442Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: ApplicationFiled: April 16, 2008Publication date: November 27, 2008Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Publication number: 20080283956Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: ApplicationFiled: April 16, 2008Publication date: November 20, 2008Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Publication number: 20080265317Abstract: A method of manufacturing a semiconductor device is disclosed and starts with a semiconductor substrate having a heavily doped N region at the bottom main surface and having a lightly doped N region at the top main surface. There are a plurality of trenches in the substrate, with each trench having a first extending portion extending from the top main surface towards the heavily doped region. Each trench has two sidewall surfaces in parallel alignment with each other. A blocking layer is formed on the sidewalls and the bottom of each trench. Then a P type dopant is obliquely implanted into the sidewall surfaces to form P type doped regions. The blocking layer is then removed. The bottom of the trenches is then etched to remove any implanted P type dopants. The implants are diffused and the trenches are filled.Type: ApplicationFiled: July 11, 2008Publication date: October 30, 2008Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventor: Richard A. Blanchard
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Patent number: 7439583Abstract: A power metal-oxide-semiconductor field effect transistor (MOSFET) cell includes a semiconductor substrate. A first electrode is disposed on the semiconductor substrate. A voltage sustaining layer is formed on the semiconductor substrate. A highly doped active zone of a first conductivity type is formed in the voltage sustaining layer opposite the semiconductor substrate. The highly doped active zone has a central aperture and a channel region that is generally centrally located within the central aperture. A terminal region of the second conductivity type is disposed in the voltage sustaining layer proximate the highly doped active zone. The terminal region has a central aperture with an opening dimension generally greater than an opening dimension of the central aperture of the highly doped zone. An extension region is disposed in the voltage sustaining region within the central aperture of the highly doped active zone.Type: GrantFiled: December 27, 2005Date of Patent: October 21, 2008Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Fwu-Iuan Hshieh
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Publication number: 20080166855Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: ApplicationFiled: March 21, 2008Publication date: July 10, 2008Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Publication number: 20080164521Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.Type: ApplicationFiled: March 21, 2008Publication date: July 10, 2008Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Patent number: 7364994Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.Type: GrantFiled: May 26, 2006Date of Patent: April 29, 2008Assignee: Third Dimension (3D) Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Koon Chong So, Brian D. Pratt
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Patent number: 7354818Abstract: A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches are formed in the termination region. The trenches of the second plurality of trenches are filled with the dielectric material.Type: GrantFiled: December 27, 2005Date of Patent: April 8, 2008Assignee: Third Dimension (3D) Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Brian D. Pratt
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Patent number: 7339252Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.Type: GrantFiled: March 20, 2006Date of Patent: March 4, 2008Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Richard A. Blanchard
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Publication number: 20070272999Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on- resistance and breakdown voltage.Type: ApplicationFiled: August 14, 2007Publication date: November 29, 2007Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.Inventor: Xing-Bi Chen