Patents Assigned to Third Dimension (3D) Semiconductor, Inc.
  • Patent number: 7271067
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: September 18, 2007
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Xing-Bi Chen
  • Patent number: 7227197
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: June 5, 2007
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Xingbi Chen
  • Patent number: 7199006
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having first and second main surfaces. The substrate has a heavily doped region of a first conductivity at the second main surface and has a lightly doped region of the first conductivity at the first main surface. The method includes providing trenches and mesas in the substrate, implanting, at an angle, a dopant of the first conductivity into a sidewall of a mesa and implanting, at an angle, a dopant of a second conductivity into the mesa at another sidewall. The method includes oxidizing the sidewalls and bottoms of each trench and tops of the mesas to create a top oxide layer, etching back the top oxide layer to expose a portion of the mesa, depositing an oxide layer to cover the etched back top layer and mesa and planarizing the top surface of the device.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: April 3, 2007
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Fwu-Iuan Hshieh
  • Publication number: 20060252219
    Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 9, 2006
    Applicant: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Fwu-Iuan HSHIEH
  • Patent number: 7109110
    Abstract: A partially manufactured semiconductor device includes a semiconductor substrate. The device includes a first oxide layer formed on the substrate, with a mask placed over the oxide-covered substrate, a plurality of first trenches and at least one second trench etched through the oxide layer forming mesas. The at least one second trench is deeper and wider than each of the first trenches. The device includes a second oxide layer that is disposed over an area of mesas and the plurality of first trenches. The device includes a layer of masking material that is deposited over a an area of an edge termination region adjacent to an active region. The area of mesas and first trenches not covered by the masking layer is etched to remove the oxidant seal. The device includes an overhang area that is formed by a wet process etch.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 19, 2006
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Fwu-Iuan Hshieh
  • Publication number: 20060205174
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Application
    Filed: May 26, 2006
    Publication date: September 14, 2006
    Applicant: THIRD DIMENSION (3D) SEMICONDUCTOR, INC.
    Inventors: Fwu-Iuan Hshieh, Koon So, Brian Pratt
  • Patent number: 7052982
    Abstract: A method of manufacturing a semiconductor device includes providing semiconductor substrate having trenches and mesas. At least one mesa has first and second sidewalls. The method includes angularly implanting a dopant of a second conductivity into the first sidewall, and angularly implanting a dopant of a second conductivity into the second sidewall. The at least one mesa is converted to a pillar by diffusing the dopants into the at least one mesa. The pillar is then converted to a column by angularly implanting a dopant of the first conductivity into a first sidewall of the pillar, and by angularly implanting the dopant of the first conductivity type into a second sidewall of the pillar. The dopants are then diffused into the pillar to provide a P-N junction of the first and second doped regions located along the depth direction of the adjoining trench. Finally, the trenches are filled with an insulating material.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: May 30, 2006
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Brian D. Pratt
  • Patent number: 7041560
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a heavily doped region of a first conductivity and has a lightly doped region of the first conductivity. The semiconductor substrate a plurality of trenches etched into an active region of the substrate forming a plurality of mesas. A preselected area in the active region is oxidized and then etched using a dry process oxide etch to remove the oxide in the bottoms of the trenches. A protective shield is formed over a region at a border between the active region and the termination region. The protective shield is partially removed from over the preselected area. Dopants are implanted at an angle into mesas in the preselected area. The plurality of trenches are with an insulating material, the top surface of the structure is planarized and a superjunction device is formed on the structure.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: May 9, 2006
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 7023069
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: April 4, 2006
    Assignee: Third Dimension (3D) Semiconductor, Inc.
    Inventor: Richard A. Blanchard