Abstract: In the manufacture of integrated circuits, an undoped wide band-gap semiconductor is used for the insulating layer to isolate the silicon substrate from the metal interconnection pattern. To provide conductive vias through the insulating layer for connection to the source and drain of the transistors of the circuit, the wide band-gap semiconductor is implanted with a dopant selectively in the portion overlying the source and drain for making the implanted portion of low resistivity and of the conductivity type of the source and drain. Preferably, carbon is the wide band-gap semiconductor and nitrogen is the dopant implanted.

Abstract: A leadframe for an integrated circuit includes a set of individual leads temporarily connected in an array; each lead having an exterior portion shaped in a standard form and an interior portion shaped to form a standard array of contacts and to have the same spring constant for deflections perpendicular to the plane of the leadframe.

Abstract: A differential amplifier (10) has two input terminals (16,18), an output terminal (20) together with power terminals (12,14). The differential amplifier comprises two or more stages with each stage having a pull-up transistor (22) and a pull-down transistor (26). The first input terminal (16) is connected to alternate stages of the amplifier (10) and the second input terminal (18) is connected to the remaining alternate stages of the amplifier (10). The gain of the various stages is determined by fabrication of the transistors, in particular, the geometries of the transistor channels. A state transition at an output terminal (20) is produced when the voltages at the input terminals (16,18) are approximately equal and the gains of the various stages are essentially equal. A state change at the output terminal (20) is caused to occur when there is a given voltage offset between the voltages at the input terminal (16,18) when the gains of the two sets of alternate stages of the amplifier (10) are made unequal.

Abstract: The voltage gain of an MOS transistor inverter stage is made independent of the device threshold voltages and of channel lengths by making the length and width of the channel region of the upper load transistor equal to the length and width of the channel region of the lower driver transistor.

Abstract: A circuit arrangement (13) for monitoring power supplies in N-channel CMOS devices, comprising elements for sampling of a bandgap voltage reference quantity (41), comparing the reference quantity to a monitored power supply voltage level (38), and compensating (49) for the offset voltage produced in the comparator element (31) conducting the comparison.

Abstract: An improved nonvolatile memory has an adaptive system to regulate the charging current supplied to store data on nonvolatile storage nodes in order to provide acceptability low strain on the tunnel oxide and to compensate for process variations and change in the Fowler-Nordheim tunnel oxide transport characteristics caused by electron trapping over time.

Abstract: A method for branding (labeling) a semiconductor chip package by warming the package prior to and subsequent to the branding resulting in a brand having greater clarity and permanency. A chip package is warmed to a temperature of about 95.degree. F. (35.degree. C.) to about 130.degree. F. (55.degree. C.) and an inked brand is applied to the warmed chip package. The branded chip package is maintained at a temperature of at least about 75.degree. F. (24.degree. C.) until the temperature is raised to a sufficient temperature to cure the branded chip package and then the branded chip package is cured.

Abstract: A programable liquid crystal arrangement including parallel transparent plates and crossed, x-y addressable electrodes with a liquid crystal material disposed therebetween, in an optical system effective for fixing patterns or words of information in selected information storage media.

Abstract: In a CMOS ROM memory arrangement, the use of the least significant column address bit to perform the dual function of even/odd bit line select and the disconnection of the selected bit line (17' and 17") from the sense amplifier (66) driven, in order to reduce its capacitive load, prior to the time of latching the information into the sense amplifier (66).

Abstract: A volatile/non-volatile integrated circuit memory cell combines a non-volatile cell (110) connected to a volatile cell (105) at a volatile node (118), in which data recall is effected through a DC-stable arrangement of transistor (142), (145) and (146) that does not employ a capacitor to hold down the storage node.

Abstract: A microcomputer includes I/O ports and registers which are mapped in memory space along with RAM and ROM and in which hardware invisible to the programmer performs a bus arbitration sequence to acquire an external bus when an off-chip reference requires the bus; and in which memory space that is used for on-chip references is recovered for use in external memory by manipulating bits in the memory address.

Abstract: A high speed CMOS NOR gate employs a pair of cross-coupled inverters and a dual set of N-channel pulldown transistors (202, 203) at each of the nodes between the two inverters, together with small pullup transistor (205) on the output terminal that is permanently energized and a switchable large pullup transistor (220) that is a link between the second inverter output and the first inverter input.

Abstract: A high speed parity circuit uses a sequence of simplified exclusive-OR circuits responsive to data input terminals containing a data signal and its complement and terminating in a sense amplifier, together with an operating sequence in which the inputs to the sequence are grounded while the data lines are first brought high and then set to the correct data state to form a pair of separate paths through the sequence when no current flows, after which set-up operation an input voltage circuit raises the voltage on one of the paths smoothly, so that the sense amplifier can respond as soon as its input is large enough, without waiting for a settling time.

Abstract: A CMOS memory arrangement having each of a plurality of data lines connected to a plurality of bitlines, at least one of said datalines having a lesser number of bitlines in order to decrease capacitance in slower signal paths and thereby increase the operating speed of the memory. A multiple input sense amplifier is connected to the plurality of data lines.

Abstract: A transistor arrangement for clamping the output node of a semiconductor memory, including an inverter to parallel with a transmission gate for producing a differential output signal.

Abstract: A system for the assembly and packaging of integrated circuits employs circuit dice that have contact pads in a standard array; a leadframe having leads configured to have the same spring constant; a method for removing selected dice from a wafer array under computer control; and a method of simultaneously bonding all leads to the die.

Abstract: A method for removing selected integrated circuit dice from a wafer array of dice sequentially moves a striker above a tape to the underside of which the array is mounted and the knocks a die down from the array of dice into a receptacle for transport to further processing stages.

Abstract: A method for inverting and handling integrated circuit dice employs rotating apparatus for rotating a chip carrier by 180 degrees to invert and transfer dice from one set of receptacles to another; together with an apparatus for precisely aligning dice resting at random positions within a set of oversized receptacles.

Abstract: CMOS memory arrangement including a circuit for setting the dataline voltage at a predetermined bias level, the circuit comprising four MOS transistors, the first, second and third and the first and fourth thereof being connected in respective series from VCC to ground, the gates of the first and second transistors being connected to ground, the bias level being established between the second and third transistors with the gate of the third transistor being connected to the node therebetween.