Abstract: A trip point clamping circuit for maintaining the voltage level at a node of connection to a sense arrangement including an inverter within defined bounds at the trip point of the inverter, the clamping circuit including a reference voltage, a source of similar current levels, a switch for turning the clamping circuit on and off, and a transistor responsive to the voltage level at said node of connection.

Abstract: A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without disturbing the CPU layout.

Abstract: An improved integrated circuit driver circuit switches a relatively large load at high speed by means of a bootstrapping capacitor that bootstraps an output transistor a fixed time after the transistor has started to drive the load.

Abstract: A synchronizing buffer arrangement for a CMOS memory with output drive transistors receiving one of a pair of input data signals, and being subject to the pull-up and pull-down support of the other of said data signals.

Abstract: A common mode gain enhancing CMOS differential sense amplifier for a static RAM memory, straddled by level shifting circuits during the respective differential inputs to the sense amplifier.

Abstract: A circuit for precharging the gates of pass transistor that will be subsequently bootstrapped employs a precharge circuit that generates a precharge pulse having magnitude greater than Vcc and distributes the pulse to a number of gate control circuits that raise the pass transistor gate voltages from a quiescent voltage level of Vcc-Vt to Vcc at a time before the bootstrapping signals arrive at the pass transistor.

Abstract: An integrated circuit contains ROM, ROM patch and RAM memories on a common substrate with a standard pinout. The ROM and RAM fill the address space allowed by the address pins. Control of the patch memory without the use of special control pins is accomplished by writing to a ROM address with the standard control pins set for a RAM write. Various control functions are made of a series of standard-cycle read and write operations.

Abstract: A microcomputer has provision for both on-chip ROM (on the same chip as the CPU) and off-chip ROM and which may operate with only on-chip ROM as only off-chip ROM has the hardware capability to disable on-chip ROM permanently, so that chips having defective ROM may be salvaged by being converted to computer chips that use only off-chip ROM.

Abstract: A simple, compact voltage reference circuit for an NMOS integrated circuit comprises a series connected depletion transistor with its gate at ground and an enhancement transistor with its gate connected to an output node between the two transistors.

Abstract: A circuit adapted for use in comparing voltages in a manner that is insensitive to power supply variations includes a pair of reference cells controlling the reference voltage of a sense amplifier through control of a pair of reference transistors and an input circuit for conditioning data having a matched input pair of transistors, so that input data will control the voltage on the input terminal of a sense amplifier in a manner such that both inputs to the sense amp track voltage, thermal and processing variations.

Abstract: An apparatus for gripping a thin flexible object located within a gripping plane having a transverse axis and a longitudinal axis perpendicular to each other and to a linear axis which is perpendicular to the gripping plane, includes first and second sets of gripper claws for gripping the object. The sets of gripper claws are located on opposite sides of the longitudinal axis and are movable between closed and open positions. Means are provided for restricting the motion of the gripper claws in a direction perpendicular to the longitudinal axis so that the gripper claws are prevented from excessive inward movement toward the longitudinal axis beyond a desired predetermined amount.

Abstract: A water purification system includes an ion-exchange unit for producing high-resistivity water, followed by ozone exposure and ultraviolet sterilizer units that oxidize organics and also reduce resistivity, followed by a vacuum degassification unit to restore high resistivity.

Abstract: A sub-circuit for discharging a relatively high voltage node in an integrated circuit includes an enhancement transistor connected between ground and an intermediate node and a depletion transistor connected between the intermediate node and the high voltage node, both of the transistors having the same gate voltage.

Abstract: A resilient stopper (40) for retaining IC's (12) in magazine (10) having a rectangular section (16) of height (h) and width (w) is disclosed. The stopper has a tubular body portion (42) of thickness (t), inner diameter (d) and width substantially (w); and a tab (50) within the stopper of thickness (b) and length (L) extending inwardly from a trailing edge area (46) of the body portion (42); wherein 2t+b>h to effect a positive interference fit of the stopper within the magazine.

Abstract: A nonvolatile memory cell (16) is fabricated on a substrate (12) and includes a source region (46) and drain regions (48, 50 and 52). Step oxides (40, 42 and 44) are fabricated respectively over the regions (46, 48 and 52). A gate oxide (58) is formed between the step oxides (40 and 42). A thin oxide tunneling element (74) is fabricated between the step oxides (42, 44) and over the drain region (50). A floating gate (38) comprising a polysilicon layer is fabricated over the step oxides (40, 42, 44), the gate oxide (58) and the tunneling element (74). An insulation layer (36) is fabricated over the floating gate (38). Finally, a control gate (34) is fabricated over the insulating layer (36) to provide capacitive coupling to the floating gate (38).

Abstract: A test circuit (10) for a semiconductor memory is provided. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).