Abstract: Embodiments of an apparatus for improving hot plate substrate monitoring and control in a lithography system are generally described herein. Other embodiments may be described and claimed.

Abstract: A method of creating and/or modifying a built-in self test (BIST) table for monitoring a thermal processing system in real-time that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response; creating a measured dynamic process response; determining a dynamic estimation error; determining if the determined dynamic estimation error can be associated with a pre-existing BIST rule in the BIST table; creating a new BIST rule when the dynamic estimation error cannot be associated with any pre-existing BIST rule in the BIST table; and stopping the process when a new BIST rule cannot be created.

Abstract: A method and system for depositing a layer from a vaporized solid precursor. The method includes providing a substrate in a process chamber of a deposition system, forming a precursor vapor by light-induced vaporization of a solid precursor, and exposing the substrate to a process gas containing the precursor vapor to deposit a layer including at least one element from the precursor vapor on the substrate.

Abstract: A solid precursor vaporization system configured for use in a deposition system, such as thermal chemical vapor deposition (TCVD), is described. The solid precursor vaporization system comprises a plurality of concentric solid precursor cylinders supported on a gas distribution plate and configured to provide a substantially constant surface area as solid precursor is consumed.

Abstract: A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.

Abstract: A method for plasma-enhanced cleaning of a system component in a batch-type processing system and a method for monitoring and controlling the cleaning. The cleaning is performed by introducing a cleaning gas in a process chamber of the batch-type processing system, forming a plasma by applying power to a system component within the process chamber, exposing a material deposit in the process chamber to the plasma to form a volatile reaction product, and exhausting the reaction product from the processing system. Monitoring of the processing system can be carried out to determine cleaning status of the processing system, and based upon the status from the monitoring, the processing system is controlled for either continuing the exposing and monitoring or stopping the cleaning process. A batch-type processing system is provided that allows plasma-enhanced cleaning of system components, and a system is provided with monitoring and controlling capability.

Abstract: A SiGe thin layer semiconductor structure containing a substrate having a dielectric layer, a variable composition SixGe1-x layer on dielectric layer, and a Si cap layer on the variable composition SixGe1-x layer. The variable composition SixGe1-x layer can contain a SixGe1-x layer with a graded Ge content or a plurality of SixGe1-x sub-layers each with different Ge content. In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate having a dielectric layer, a Si-containing seed layer on the dielectric layer, a variable composition SixGe1-x layer on the seed layer, and a Si cap layer on the variable composition SixGe1-x layer. A method and processing tool for fabricating the SiGe thin layer semiconductor structure are also provided.

Abstract: A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.

Abstract: Apparatus and methods to compensating for radial non-uniformities in the plasma sheath at a substrate held by an electrostatic chuck in a plasma processing system. The substrate is held by a substrate-supporting surface of the electrostatic chuck. The substrate-supporting surface is modified by providing a pattern of features characteristic of a compensating structure that corrects the radial non-uniformities in the plasma sheath and then covering the features conformally with a planarization coating of a dielectric material. The dielectric material fills and covers the pattern of features to provide multiple parallel capacitances defining the compensating structure. The pattern of features characterizing the compensating structure may be determined from a radial non-uniformity in a plasma-related parameter at the substrate-supporting surface.

Abstract: A magnetically enhanced plasma is produced with a permanent magnet assembly adjacent to a radio frequency (RF) biased wafer support electrode in a vacuum processing chamber of a semiconductor wafer processing apparatus. An annular peripheral region is provided on the wafer support around the perimeter of the wafer being processed. A magnet arrangement using a plurality of magnet rings forms a magnetic tunnel over the peripheral region at which the plasma is generated away from the wafer. The magnetic field has components parallel to the substrate support surface over the annular peripheral region but which are perpendicular to the surface at the wafer. Preferably, the magnetic field has a flat portion parallel to the support surface in the peripheral region. Plasma propagates by diffusion from the peripheral region across the wafer surface. The magnets can be manipulated to optimize plasma uniformity adjacent the substrate being processed.

Abstract: A method of securing a substrate in a semiconductor processing machine. The method includes moving latch bodies between latched and unlatched positions while permitting contact between a clamping member of each latch body and the substrate only if the latch bodies are substantially in the latched position. In the latched position, the clamping members apply a clamping force effective to secure the substrate. Generally, contact is prevented by engagement between a support member and an ramp that is inclined such that the clamping member descends toward the substrate as the latch body moves from the unlatched position to the latched position and only contacts the substrate as the latched position is established.

Abstract: A processing system for processing a substrate with a plasma comprises a processing chamber defining a processing space for containing a substrate to be processed with a plasma formed within the chamber. A dielectric window interfaces with the processing chamber proximate the processing space. A core element formed of a material having a high magnetic permeability is positioned outside of the chamber proximate the dielectric window, and an electrically conductive element surrounds a portion of the core element of high magnetic permeability. The conductive element, when electrical current is conducted thereby, is operable for coupling a magnetic flux into the chamber through the dielectric window for affecting a plasma in the processing space. The core element is configured for directing a portion of the magnetic flux in a direction toward the dielectric window to efficiently couple the channeled flux into the processing chamber through the dielectric window.

Abstract: A method of plasma generation is provided in which the application of a static magnetic field perpendicular to the direction of the RF electric field allows for the propagation of an electromagnetic wave from a coil outside the chamber, through a dielectric window and into the plasma. The RF electric field and the DC magnetic field are both in the plane of the dielectric window in what may be called a planar helicon configuration. Due to magnetic field effects, the electromagnetic wave excites an electron cyclotron wave that heats the electrons by mode conversion of the whistler wave a few centimeters from the dielectric window where a mode conversion relationship among characteristic antenna wavelength, generator frequency, magnetic field strength and plasma electron density is satisfied The curvature of the magnetic field lines generates plasma flows that expel the plasma towards the processing space.

Abstract: Method and apparatus for controlling the migration of reaction by-product gases from a chemical vapor deposition (CVD) process chamber to a transfer vacuum chamber shared by other process chambers. Separate regulated flows of purge gas are provided to the CVD process chamber and the transfer vacuum chamber before establishing a pathway for substrate transfer. A pressure differential is created between the transfer vacuum chamber and the CVD process chamber that reduces or prevents the migration of CVD reaction by-product gases arising from the establishment of the substrate transfer pathway. While the pathway is established, a directional flow of purge gas is maintained from the transfer vacuum chamber into the CVD process chamber.

Abstract: Apparatus and methods for a wafer handling system that manipulates semiconductor wafers. The invention includes an end effector having a vacuum chuck, an internal vacuum plenum, and flow diverters positioned within the vacuum plenum that define vacuum distribution channels coupled in fluid communication with vacuum ports of the vacuum chuck. The invention also includes a vacuum chuck having flow diverters positioned in one or more internal vacuum plenums that are in fluid communication with the vacuum ports of the vacuum chuck. The flow diverters adjust the vacuum pressure supplied to the vacuum ports such that, as vacuum ports are occluded by the wafer, the vacuum pressure is preferentially applied to unblocked vacuum ports for increasing the attractive force applied to unengaged portions of the wafer. The apparatus of the present invention has particularly utility for securing thin semiconductor wafers with a significant warpage.

Abstract: To protect a dielectric window in an inductively coupled plasma reactor from depositions of coating or etched material from the plasma, a dielectric insert is placed inside of the chamber closely adjacent the window. Where a slotted shield inside of the window protects the window from deposition, but has slots through which some material can pass in a direction toward the window, the insert is placed between the window and the shield. The insert is formed of a material that is compatible with the process being carried out on a semiconductor wafer within the chamber. Where the window and shield are planar, an unprocessed wafer of the same type and material as the wafer being processed is used for the insert.

Abstract: A method for characterizing the performance of an electrostatic chuck prior to installing the chuck in the vacuum chamber of a semiconductor processing system in a production line. One or more characteristics of the electrostatic chuck are measured and compared with the known characteristics of a reference chuck. The comparison indicates the performance of the chuck and projects the performance of the chuck in an actual operating environment. The characteristics that are measured include the chuck impedance, the current-voltage characteristic of the chuck, the local plasma density proximate the support surface of the chuck, and the cooling or heating rate of the chuck.

Abstract: Deposition of ionized material at a beveled or non-flat edge of a semiconductor wafer and the etching by the ionized material at such edge is controlled in a high density plasma processing machine by surrounding the wafer with a conducting ring to affect sheath potential and deflecting the ions of the material in such a way that the deposition and etching rate changes in a controlled way over the region immediately adjacent the wafer edge. The ring may be biased in several ways to control the ion flux to the wafer edge.

Abstract: A method and apparatus are provided by which the effects of the plasma power RF source and substrate bias are decoupled to reduce the effect of plasma power on the wafer bias and to improve process control. A technique is provided that includes establishing a high density plasma adjacent to a semiconductor wafer, such as by inductive coupling, at some RF plasma excitation frequency, preferably at a frequency between 50 kHz and 50 MHz. RF power from a bias power source is applied to a chuck on which a wafer is supported which exhibits high capacitance between the RF feed of the bias power source and the wafer. The RF power to the substrate support is applied through a matching unit at a frequency that is identical to or close to that of the frequency of the primary power to the plasma.

Abstract: A semiconductor wafer holding assembly that secures a semiconductor wafer for wafer handling by a semiconductor processing machine. The wafer holding assembly includes a clamp ring that is mounted to a support frame and that has a wafer-engaging surface. A plurality of latch assemblies are mounted about the periphery of the clamp ring and adjacent to the wafer-engaging surface. Each latch assembly includes a latch body that carries a clamping roller assembly and a supporting roller assembly. A rolling element of the supporting roller assembly rolls along a circular path on an inclined surface on the clamp ring as the latch body is rotated through a pivot arc between an unlatched position and a latched position. Unless the latch body is positioned in the latched position, the rolling engagement between the supporting roller assembly and the inclined surface suspends the rolling element of the clamping roller assembly above the wafer surface until the latch body is in the latched position.