Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: A failure point identifying method applicable to various defects and capable of promptly identifying a defect point. An LSI tester 4 sequentially impresses test vectors stored in a test vector file 1 across input terminals of a loaded LSI 5 to measure an Iddq value. A test vector number of a test vector which produced an abnormal Iddq value is delivered to a faulty block extractor 2. The faulty block extractor 2 performs logic simulation to find the input logic of each block of the LSI 5 when each test vector stored in the test vector file 1 is entered to the input terminals of the LSI 5. Moreover, a dump list associating each test vector number with the input logic is prepared from block to block. The faulty block is then identified based on the dump list of each block and the test vector number deliver from the LSI tester.

Abstract: A photoelectric converter made of a semiconductor transistor of the type that the potential of a control electrode region is controlled through a capacitor, wherein the capacitor is constructed such that the capacitor electrode faces the control electrode region with an insulating layer interposed therebetween, and at least the portion of the control electrode region which faces said capacitor electrode is a region having a high impurity density.