Patents Assigned to Tokyo Shibaura Electric Co., Ltd.
  • Patent number: 4290828
    Abstract: A bimetal is disclosed having a high, rapid deflection over a specified temperature range, including a high expansion metal alloy component having a high thermal expansion coefficient that changes rapidy at 50.times.10.sup.-6 /.degree.C. or greater at a temperature of between about 100.degree. C. and 250.degree. C. and containing from 15-30% by weight of manganeses, the balance of iron. The second component has a substantially constant thermal expansion coefficient regardless of the temperature change, and is preferably a stainless steel. These bimetals are used in circuit breakers, thermal protectors and the like.
    Type: Grant
    Filed: July 11, 1979
    Date of Patent: September 22, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Tatsuyoshi Aisaka, Mitsuo Kawai, Fumio Mori, Shinzo Sugai
  • Patent number: 4284998
    Abstract: A junction type field effect transistor comprises a semiconductor layer of one conductivity type acting as a drain region, a source region of said one conductivity type formed to a prescribed depth from the surface of the semiconductor layer, an insulation layer formed to a prescribed depth from the surface of the semiconductor layer to surround the source region, and a gate region of the opposite conductivity type formed in the proximity of the sorce region. The insulation layer and source region are formed to substantially the same depth.
    Type: Grant
    Filed: August 28, 1978
    Date of Patent: August 18, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Noboru Fuse, Kenichi Muramoto, Keizo Tani, Masaaki Iwanishi
  • Patent number: 4284432
    Abstract: Ceramic powder material mainly consists of silicon nitride wherein the content of oxygen combined with generally unavoidable impurities as measured by activation analysis accounts for less than 2% by weight. The above-mentioned ceramic powder material can also be prepared preferably by the method which comprises the step of heating raw ceramic powder material mainly consisting of silicon nitride to 1,400.degree. C. to 1,900.degree. C. in the presence of a separately prepared nonsintered molding of ceramic material or sintered molding of ceramic material having a porosity of at least 10%.
    Type: Grant
    Filed: September 21, 1979
    Date of Patent: August 18, 1981
    Assignee: Tokyo Shibaura Electric Co. Ltd.
    Inventors: Katsutoshi Nishida, Michiyasu Komatsu, Tadashi Miyano
  • Patent number: 4285038
    Abstract: The system is constructed to operate to mutually transfer information between a processor and a terminal device via a first-in/first-out type stack. Signal generators are provided on the input and output sides of the stack for generating signals corresponding to the EMPTY and FULL statuses of the stack thereby controlling to inhibit or commence the transfer of the information in response to the direction of transfer of the information and the status of the stack.
    Type: Grant
    Filed: June 21, 1979
    Date of Patent: August 18, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Seigo Suzuki, Seiji Eguchi, Yoshiaki Moriya
  • Patent number: 4282860
    Abstract: A hot air type solar heat-collecting apparatus comprises a first transparent plate, a second transparent film located thereunder, and a corrugated metal plate mounted on the underside of a second transparent film to absorb the sunlight. The metal plate forms a first group of air passages on the upperside thereof and a second group of air passages on the underside thereof.
    Type: Grant
    Filed: November 29, 1979
    Date of Patent: August 11, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Hisao Koizumi, Yoshinosuke Kawada, Koichi Matsui
  • Patent number: 4282438
    Abstract: A computerized tomography system and method using penetrating radiation having a radiation source for radiating penetrating radiation into the interior of a thin sliced layer portion of a subject, in a manner that it expands substantially in a fanned fashion, a detector for substantially dividing the radiation after passing through said sliced layer portion into a plurality of radiation beams diverging at a defined angle, thereby detecting the intensity of said beams, a moving unit for substantially linearly scanning each of said beams at least once in a direction transverse of said sliced layer portion, a data processing unit for reconstructing an image of said sliced layer portion on the basis of detected data delivered from said detector, and a display unit for displaying said image on the basis of the results of said reconstruction.
    Type: Grant
    Filed: February 14, 1978
    Date of Patent: August 4, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Susumu Nishida, Tamon Inouye, Tadatoki Yoshida, Kiyoto Saito
  • Patent number: 4279022
    Abstract: An electronic calculation/memorandum apparatus comprises: a main memory; a key input unit including character keys, numerical keys, symbol keys, and a character mode selection key, a data write-in key for the main memory, and a data read-out key for the main memory; means for setting the main memory to a write mode through the operation of the write-in key; means for writing index data including characters and/or symbols inputted from the key input unit and numerical data associated with the index data in the order of inputting of them into the input key, into the main memory successively from the head address and the succeeding ones; means for alternately reading out all the index data and numerical data stored in the main memory in the order of the writing thereof in the read-out mode and for displaying them; means for retrieving the numerical data corresponding to the index data inputted from the main memory and for displaying it; and a unit for performing calculation on the basis of numerical data inputte
    Type: Grant
    Filed: May 29, 1980
    Date of Patent: July 14, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Kazuhiro Abe
  • Patent number: 4275430
    Abstract: A snubber circuit is connected between the anode and cathode of a gate turn-off (GTO) thyristor. To the GTO thyristor a saturable reactor is connected in series. A gate off signal is supplied to the gate of the GTO thyristor and to the saturable reactor as backward current to reset the saturable reactor.
    Type: Grant
    Filed: December 21, 1977
    Date of Patent: June 23, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Nagataka Seki, Yukio Watanabe
  • Patent number: 4268904
    Abstract: An interrupt control method for a multiprocessor system including a plurality of microprocessors wherein sections of a main memory, which is shared among the processors of the system, are allocated to store entry address data pointing to a plurality of interrupt-servicing programs for each of the several processors of the system. Interrupt commands are coded to designate different interrupt levels which are compared against mask flag bits and a master mask flag bit unique to each processor to determine which processor will respond to the interrupt command. The processors are arranged in a fixed priority sequence and respond to an interrupt command in a designated priority order. Controls are provided to prevent a processor which is executing an interrupt-servicing program from responding to a subsequent interrupt command until execution of the interrupt-servicing program is completed.
    Type: Grant
    Filed: December 13, 1978
    Date of Patent: May 19, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Seigo Suzuki, Seiji Eguchi
  • Patent number: 4264968
    Abstract: There is provided an electronic timepiece basic circuit comprising a pulse generating circuit for generating 1 Hz pulses, a first terminal group having a plurality of terminals including a terminal connected to the output terminal of the pulse generating circuit, a second terminal group having terminals to be connected to the terminals of the first terminal group, respectively, 10 scale counters coupled with the second terminal group, 6 scale counters connected to the 10 scale counters, a display unit, and a decoder which is coupled with the 10 scale counters and the 6 scale counters and decodes the contents of the 10 and 6 scale counters and delivers the decoded contents to the display unit. The first and second terminal groups are properly coupled to each other. The combination of the 10 scale counters and the 6 scale counters is properly modified so as to form a 12, 24, or 60 scale counter, as necessary.
    Type: Grant
    Filed: December 27, 1977
    Date of Patent: April 28, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yasoji Suzuki, Fuminari Tanaka, Yasushi Sato
  • Patent number: 4263067
    Abstract: A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.
    Type: Grant
    Filed: February 21, 1980
    Date of Patent: April 21, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kouichi Takahashi, Hidekuni Ishida, Toshio Yonezawa
  • Patent number: 4260906
    Abstract: A semiconductor device comprises a P type semiconductor substrate; an N type layer buried in the P type substrate; and an N type isolating region extending from the surface of the P type substrate to the N type buried region to provide a P type isolated region in the P type substrate. In the P type isolated region marked off by the N type isolating region is formed a first N type region so as not to contact the N type isolating region and buried region and a P type second region is diffused in the first N type region. A logic circuit is constituted by a first vertical PNP transistor formed of the P type second region, first N type region and P type isolated region and a second vertical NPN transistor formed of the first N type region, P type isolated region and N type buried region.
    Type: Grant
    Filed: May 15, 1978
    Date of Patent: April 7, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Yukuya Tokumaru, Masanori Nakai
  • Patent number: 4259292
    Abstract: A gas detecting element comprising a hollow cylindrical insulative body, a pair of electrodes provided on the outer periphery of the insulative body, a gas detecting body covering up the outer periphery of the insulative body and the electrodes, a catalyst layer made of a catalytic material and coated on said gas detecting body, thereby covering up the surface of said gas detecting body, and a heater disposed in the hollow of the insulative body. When the gas detecting element comes into contact with a gas, the surface resistance of the gas detecting body varies, thereby detecting the gas.
    Type: Grant
    Filed: January 31, 1978
    Date of Patent: March 31, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Noboru Ichinose, Hideo Okuma, Yuji Yokomizo, Takashi Takahashi, Mieko Nishihara, Masaki Katsura
  • Patent number: 4257043
    Abstract: Disclosed is a multichannel display device which is so constructed that the waveform of input signal of each channel displayed on the cathode ray tube may be enlarged or reduced in the horizontal sweep direction or the horizontal direction by setting a sampling time interval for sampling the input signal of the channel to store the same in a corresponding one of plural memory units provided for each channel, a reading time for reading a sampled data stored in the corresponding memory, and a horizontal sweeping speed or one-sweep time of a cathode ray tube for displaying the waveform of the input signal in accordance with the sampled data as read, so as to permit these three factors to have an interrelation determined with respect to the channel.
    Type: Grant
    Filed: March 22, 1978
    Date of Patent: March 17, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Masayoshi Tsuchiko
  • Patent number: 4255136
    Abstract: A furnace for the heat treatment of wire materials, comprising a cylindrical furnace body having holes at both ends through which a wire material is inserted into and out of the furnace body, a combustion chamber formed within the furnace body, a burner provided at one end portion of the furnace body and adjacent to the combustion chamber, and a discharge pipe mounted near the downstream edge of the combustion chamber for discharging the waste gas. The burner comprises a free space through which the wire material is inserted, a fuel-air mixture chamber surrounding the free space, and injection nozzles communicating with the fuel-air mixture chamber and serving to inject the mixture into the combustion chamber. The injection nozzles are arranged to permit the injected streams of fuel-air mixture to make whirling motions in the same direction along the inner wall of the combustion chamber in such a manner as to be free from direct contact with the wire material running along the axis of the combustion chamber.
    Type: Grant
    Filed: February 13, 1980
    Date of Patent: March 10, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Teruo Suzuki, Shigeru Kuwabara
  • Patent number: 4253338
    Abstract: An ultrasonic diagnostic equipment of linear electric scanning type includes a plurality of pulse generators for supplying electric pulses to a plurality of ultrasonic transducers disposed on a plane, gate circuits for driving the pulse generator, a plurality of analogue switching circuits for selecting the reflected ultrasonic pulse signals received by the ultrasonic transducers, and a control circuit for controlling these pulse generators and switching circuits. The control circuit synchronizingly controls the operations of the gate circuits and analogue switching circuits in order to operate a given number of ultrasonic transducers of the plural of the ultrasonic transducers. The pulse generator and switching circuit are provided corresponding to each transducer.
    Type: Grant
    Filed: April 27, 1977
    Date of Patent: March 3, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kazuhiro Iinuma, Takeshi Kidokoro, Kinya Takamizawa
  • Patent number: 4252840
    Abstract: A method of manufacturing a semiconductor device which comprises the steps of forming an insulating layer on a semiconductor substrate; removing that region of the insulating layer which is to be used for an electrode contact spot, thereby forming a hole for electrode contact, removing that region of the insulating layer on which wiring is to be laid to the intermediate section of the thickness of said insulating layer, thereby providing a stepped section between the bottom of the specified wiring region of said insulating layer thus removed and the surface of said insulating layer; and depositing a metal layer all over the surface of the insulating layer and then cutting off at said stepped section the portion of the metal layer formed on the specified wiring region of said insulating layer from the other portions of the metal layer remaining on the surface of the insulating layer, thereby providing the prescribed wiring.
    Type: Grant
    Filed: December 5, 1977
    Date of Patent: February 24, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Kenji Minami
  • Patent number: 4252595
    Abstract: An etching device uses a gas activated by a plasma for etching semiconductor elements. The apparatus includes etching chamber in which semiconductor elements are horizontally held by a supporting plate or conveyer and etched. The etching gas introduced from the upper side of the semiconductor element to the down side thereof through holes formed in the supporting plate or conveyer.
    Type: Grant
    Filed: March 28, 1978
    Date of Patent: February 24, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Shinichi Yamamoto, Yasusuke Sumitomo, Yasuhiro Horiike, Masahiro Shibagaki
  • Patent number: 4251862
    Abstract: A microprogram control system comprising first and second control memories each supplied with microinstructions. The microprogram control system usually executes a microinstruction of a prescribed bit length read out of the first control memory. The first control memory contains data instructing the use of the second control memory. When the first control memory sends forth data instructing the use of the second control memory, a composite microinstruction of larger bit length is executed. The composite microinstruction is formed of a microinstruction read out of the first control memory and a microinstruction read out of the second control memory.
    Type: Grant
    Filed: January 29, 1980
    Date of Patent: February 17, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Masaki Murayama
  • Patent number: 4250370
    Abstract: A control device adapted to control cooking time and power of an electric cooking device. By depressing entry keys on a control panel a desired cooking time data and power level setting data are entered in first and second shift registers respectively. Next when a cooking start key is depressed the electric cooking device starts its operation at a power corresponding to the power level setting data and the down count operation of the time data in the first shift register is started. When the time data in the first shift register becomes zero due to the down count operation the cooking device stops its operation. The data in the first and second shift registers are displayed by digital indicators. The time data in the first shift register is detected whether or not it has an erroneous digit or digits and any detected erroneous digit or digits are blanked or flashed on the digital indicators.
    Type: Grant
    Filed: August 23, 1978
    Date of Patent: February 10, 1981
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Masayuki Sasaki, Shuichi Gotou