Abstract: The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board.

Abstract: A semiconductor packaging method and a semiconductor package device are provided. The packaging method includes providing a chip. The chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; a plurality of pads disposed at the front surface of the chip substrate and around the photosensitive region, where the chip substrate contains a through-hole formed from the back surface of the chip substrate, and the plurality of pads are exposed from the through-hole; and a transparent protection layer over the front surface of the chip substrate, where the transparent protection layer covers the photosensitive region and the plurality of pads. The packaging method also includes electrically connecting each pad of the plurality of pads to a circuit board through a corresponding metal rewiring layer in the through-hole.

Abstract: Packaging structure is provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.

Abstract: Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Abstract: A packaging structure includes a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface, and the first surfaces of the conductive connection pillars are fixed to a surface of the semiconductor chip. The packaging structure also includes a carrier plate. The carrier plate is disposed opposite to the semiconductor chip. The conductive connection pillars are located between the semiconductor chip and the carrier plate, and the second surfaces face the carrier plate. The packaging structure further includes solder layers located between the carrier plate and the second surfaces, and a barrier layer located on the surface of the carrier plate around the solder layers.

Abstract: Packaging structure and method of forming a packaging structure are provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.

Abstract: Semiconductor chip package device and semiconductor chip package method are provided. The semiconductor chip package device includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves disposed at ends of the lead frame. The chips are electrically connected to the lead frame. The encapsulating layer is formed by using an encapsulating material to encapsulate the chips and at least a portion of the lead frame. The first grooves are filled with the encapsulating material. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Abstract: Packaging structure and method for forming a packaging structure are provided. A bonding layer is formed on the substrate. An improvement layer is formed on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are provided and include functional surfaces. The chips are mounted on the substrate by bonding the functional surfaces of the chips to the bonding layer through the openings. Top surfaces of the chips are lower than or flush with a top surface of the improvement layer.

Abstract: Semiconductor chip package array is provided. The semiconductor chip package array includes: a lead frame, chips, an encapsulating layer, and an electroplating layer. The lead frame includes a first surface, a second surface, a plurality of support units arranged in a matrix, first grooves, second grooves, and third grooves. The first grooves are connected to the second grooves to form through holes and the third grooves are connected to adjacent support units of the plurality of support units. The chips are disposed on and electrically connected to the plurality of support units. An encapsulating material encapsulates the chips and at least a portion of the plurality of support units, and fill the first grooves to form the encapsulating layer. The electroplating layer is disposed on the second surface of the lead frame, and extends into the third grooves or into the third grooves and the second grooves.

Abstract: The present disclosure provides a package structure and its packaging method. The packaging method includes: providing a bonding layer on a substrate; forming an improvement layer on the bonding layer, where the improvement layer has openings, and bottoms of the openings expose a surface of the bonding layer; providing chips, each including a non-functional surface; and mounting the chips by attaching the non-functional surface to the bonding layer at the bottoms of the openings.

Abstract: A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate.

Abstract: A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least one flip package layer on the first functional surface of the packaging substrate and forming at least one wiring and package layer on the flip package layer. The flip package layer is formed by subsequently forming a flip mounting layer, an underfill, a sealant layer, and a wiring layer; and the wiring and package layer is formed by subsequently forming a straight mounting layer, a sealant layer, and a wiring layer. Further, the method includes planting connection balls on the second functional surface of the packaging substrate.

Abstract: Testing probe and semiconductor testing fixture, and their fabrication methods are provided. A plurality of first testing pins is formed on the substrate, each first testing pin including a first testing terminal on a top and a first connection terminal on a bottom. An insulating layer is formed on a sidewall surface of each first testing pin. A number of second testing pins are formed on the insulating layers, each second testing pin including a second testing terminal on a top thereof and a second connection terminal on a bottom thereof. A first concave surface is formed on a top of the second testing terminal, and surrounds a corresponding first testing pin.

Abstract: A testing probe is provided. The testing probe includes a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.

Abstract: The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.

Abstract: A semiconductor testing fixture is provided. The semiconductor testing fixture comprises a substrate having a surface; a plurality of testing probes formed on the surface of the substrate; and a dielectric layer filling space between adjacent testing probes and covering side surfaces of the plurality of testing probes formed on the surface of the substrate.

Abstract: Testing probe and semiconductor testing fixture, and their fabrication methods are provided. A testing probe may configure a chamber through an insulating body. A first testing pin is disposed inside the chamber of the insulating body. The first testing pin includes: a first testing terminal on one end of the first testing pin and a first connection terminal on another end of the first testing pin. An elastic member is disposed inside the chamber and attached to the first testing pin to drive an upward or downward movement of the first testing pin along the chamber. A second testing pin is disposed around an outer sidewall surface of the insulating body enclosing the first testing pin. The second testing pin includes a second testing terminal on one end of the second testing pin and a second connection terminal on another end of the second testing pin.

Abstract: A semiconductor testing fixture is provided. The semiconductor testing fixture includes a substrate having a plurality of testing regions; and a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions. Etch of the testing probes comprises a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.

Abstract: A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on the top of the conductive metal pad with the metal core protruding from the surface of the substrate; then, forming an under bump metal layer on the top surface and the side surface of the metal core; and finally, forming a bump structure on the top of the under bump metal layer.

Abstract: Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole.