Abstract: Testing probe and semiconductor testing fixture, and their fabrication methods are provided. A testing probe may configure a chamber through an insulating body. A first testing pin is disposed inside the chamber of the insulating body. The first testing pin includes: a first testing terminal on one end of the first testing pin and a first connection terminal on another end of the first testing pin. An elastic member is disposed inside the chamber and attached to the first testing pin to drive an upward or downward movement of the first testing pin along the chamber. A second testing pin is disposed around an outer sidewall surface of the insulating body enclosing the first testing pin. The second testing pin includes a second testing terminal on one end of the second testing pin and a second connection terminal on another end of the second testing pin.

Abstract: The present disclosure discloses a fabrication method for wafer-level packaging, comprising: forming a first photoresist on a first chip and a plurality of first openings at the first photoresist to expose a functional surface of the first chip, forming an under-bump metal layer on the functional surface exposed through the plurality of first openings, and removing the first photoresist; connecting a functional solder bump of a second chip to the under-bump metal layer on the first chip; forming a filling layer between the first chip, and the second chip; and forming a connecting member on the first chip, wherein a solder ball is disposed at a top surface of the connecting member, and an apex of the solder ball is higher than a top surface of the second chip.

Abstract: A semiconductor testing fixture is provided. The semiconductor testing fixture includes a substrate having a plurality of testing regions; and a plurality of testing probes with a predetermined distribution pattern formed on the substrate in each of the plurality of testing regions. Etch of the testing probes comprises a first testing tip; an insulation layer formed on a side surface of the first testing tip; and a second testing tip being coaxial with the first testing tip and surrounding the first testing tip formed on a side surface of the insulation layer.

Abstract: A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on the top of the conductive metal pad with the metal core protruding from the surface of the substrate; then, forming an under bump metal layer on the top surface and the side surface of the metal core; and finally, forming a bump structure on the top of the under bump metal layer.

Abstract: Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole.

Abstract: A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on the top of the conductive metal pad with the metal core protruding from the surface of the substrate; then, forming an under bump metal layer on the top surface and the side surface of the metal core; and finally, forming a bump structure on the top of the under bump metal layer.

Abstract: Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode.