Abstract: A PWM/PFM control circuit has a differential time generating means for forming a differential time signal representing a differential time corresponding to a difference between the pulse width of a PWM control signal and the pulse width of a PFM control signal on condition that the pulse width of the PWM control signal is smaller than the pulse width of the PFM control signal, and the oscillation frequency of a reference signal serving as a reference for forming the PWM control signal is controlled based on the differential time signal to a low value in accordance with the differential time.
Abstract: A switching power supply circuit comprises: current detection means for detecting a current flowing through an inductor; current holding means for holding the current flowing through the inductor over a past predetermined period; and current superposition means for adding to an output of an error amplifier a current superposition signal which makes an adjustment, based on a present current information signal as an output signal of the current detection means, such that the ON-period of a switching signal of a PWM comparator is shortened, and also makes an adjustment, based on a past current information signal as an output signal of the current holding means, such that the ON-period of the switching signal of the PWM comparator is lengthened.
Abstract: A switching power supply circuit has a current mode control circuit including current detection means, and current mode signal generation means for generating a current mode signal being a drain current of a first MOS transistor obtained by supplying a first current information signal, which is an output signal of the current detection means, to the gate of the first MOS transistor, and by connecting a first resistance to the source of the first MOS transistor, and supplies the current mode signal to a feedback control system of the switching power supply circuit.
Abstract: A semiconductor device includes: a semiconductor element 2 bonded on a first metallic layer; a wire 4 for electrically connecting an electrode pad of the semiconductor element to a second metallic layer; and a resin package 7 for sealing said semiconductor element. Rear surfaces of the first metallic layer 8a and the second metallic layer 8b are flush with a bottom of said resin package.